Question: Writing text file based TestBenches vs. Waveform file based simulation.

Discussion in 'VHDL' started by BLF, Aug 6, 2004.

  1. BLF

    BLF Guest

    I just wanted to know if more people are moving toward waveform based
    simulations. From my point of view, drawing the actual waveforms to
    perform the testing (as you can do in Aldec 6.2) makes life much
    easier, especially since Aldec allows you to save the waveform as a
    testbench text file. Am I correct in saying that you can't graphically
    enter a waveform in ModelSim?

    Writing testbench files to seem very tedious and it takes a great deal
    of knowledge to write one properly and a lot of time. On the other
    hand creating a waveform is quicker and more intuitive.

    Just wanted to know what others think about this subject.

    BLF
     
    BLF, Aug 6, 2004
    #1
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  2. On Fri, 06 Aug 2004 15:24:47 -0400, BLF <> wrote:

    >I just wanted to know if more people are moving toward waveform based
    >simulations.


    I've spent the last few years moving away from them.

    >From my point of view, drawing the actual waveforms to
    >perform the testing (as you can do in Aldec 6.2) makes life much
    >easier, especially since Aldec allows you to save the waveform as a
    >testbench text file.


    I reckon it's a PITA, but I know some people like it.

    > Am I correct in saying that you can't graphically
    >enter a waveform in ModelSim?


    Yes, as far as I know. Howvere, there are commercially
    available tools that will allow you to create waveforms
    graphically, and then will automatically generate VHDL
    or Verilog testbench code that creates the same
    waveforms in simulation; of course, these tools can
    be used with any simulator.

    >Writing testbench files to seem very tedious and it takes a great deal
    >of knowledge to write one properly and a lot of time. On the other
    >hand creating a waveform is quicker and more intuitive.


    And desperately inflexible. Can you draw for me a test waveform
    that...
    - is parameterisable for data bus width?
    - contains subroutine calls, so that I can do the same
    operation over and over again with different values (think
    read and write cycles on a bus)?
    - can have randomised time delays built-in?
    - generates test cycles automatically?
    - can automatically predict and check the expected outputs
    from the device under test?
    All the above, and more, can be done in a VHDL test bench with
    no difficulty in principle (although, as usual, in practice
    it can get pretty complicated if your device under test is
    non-trivial).

    I agree that writing VHDL code to generate a simple stream of
    pulses can seem tedious at first. But you have the power of
    a programming language behind it, which can give you immense
    flexibility and gives you lots of payback for your initial
    investment in creating a suitable stimulus generator (often
    known as a BFM or Bus Functional Model).

    Jonathan Bromley
     
    Jonathan Bromley, Aug 6, 2004
    #2
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  3. Re: Question: Writing text file based TestBenches vs. Waveform filebased simulation.

    BLF <> writes:

    > I just wanted to know if more people are moving toward waveform based
    > simulations. From my point of view, drawing the actual waveforms to
    > perform the testing (as you can do in Aldec 6.2) makes life much
    > easier, especially since Aldec allows you to save the waveform as a
    > testbench text file. Am I correct in saying that you can't graphically
    > enter a waveform in ModelSim?


    Drawing waveforms take a lot of time, is error prone, and is only
    feasible (in my mind) with very simple protocols. I'f you're thinking
    waveforms, you're thinking too small scale.

    Creating hundreds of testcases, totalling maybe a full second of
    simulation (with 100-300MHz clocks) can only be done using script
    based (and hence, text based) verification.

    I can't imagine using waveforms to enter even a single 1518 byte
    Ethernet frames, including correct FCS.

    Regards,


    Kai
     
    Kai Harrekilde-Petersen, Aug 6, 2004
    #3
  4. BLF

    Jim Lewis Guest

    Re: Question: Writing text file based TestBenches vs. Waveform filebased simulation.

    BLF,
    Using a VHDL subprogram to encapsulate a
    sequence/waveform/transaction will give a great
    deal of flexability. Generating the initial code
    is usually straight forward and does not require a
    graphical entry tool.

    This is just a starting point. If you are interested in more,
    see my DVCon Paper titled, "Accelerating Verification Through
    Pre-Use of System-Level Testbench Components." It is
    available at:
    http://www.synthworks.com/papers/

    If you want to learn more about transaction based subprograms
    and models, take our VHDL Testbenches and Verification class:
    http://www.synthworks.com/vhdl_testbench_verification.htm

    Cheers,
    Jim
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

    BLF wrote:
    > I just wanted to know if more people are moving toward waveform based
    > simulations. From my point of view, drawing the actual waveforms to
    > perform the testing (as you can do in Aldec 6.2) makes life much
    > easier, especially since Aldec allows you to save the waveform as a
    > testbench text file. Am I correct in saying that you can't graphically
    > enter a waveform in ModelSim?
    >
    > Writing testbench files to seem very tedious and it takes a great deal
    > of knowledge to write one properly and a lot of time. On the other
    > hand creating a waveform is quicker and more intuitive.
    >
    > Just wanted to know what others think about this subject.
    >
    > BLF
     
    Jim Lewis, Aug 7, 2004
    #4
  5. BLF <> wrote:

    >Writing testbench files to seem very tedious and it takes a great deal
    >of knowledge to write one properly and a lot of time. On the other
    >hand creating a waveform is quicker and more intuitive.


    If you like drawing waves, maybe you
    would like a vhdl process like this:

    begin -- mk_waves
    init;
    tic;
    tic;
    dat_s <= x"42";
    toggle(stb_s);
    tic;
    dat_s <= x"AA";
    toggle(stb_s);
    tic;
    dat_s <= x"00";
    tic;
    done_s <= true;
    tic;
    tic;
    end process mk_waves;

    See the details below.

    -- Mike Treseler

    ------------------------------------------------------
    -- vsim waves -do "radix hex; add wave \*;run -all";
    library ieee;
    use ieee.std_logic_1164.all;

    entity waves is
    end entity waves;

    architecture sim of waves is
    -- wires
    signal clk_s : std_ulogic;
    signal rst_s : std_ulogic;
    signal done_s : boolean;
    signal dat_s : std_logic_vector(7 downto 0);
    signal stb_s : std_ulogic;

    begin -- architecture sim
    -- "Draw" some waves Fri Aug 6 16:01:26 2004 Mike
    mk_waves : process is

    procedure tic is
    begin
    wait until rising_edge(clk_s);
    end procedure tic;

    procedure toggle (signal arg : inout std_ulogic) is
    begin
    tic;
    arg <= '1';
    tic;
    arg <= '0';
    end procedure toggle;

    procedure init is
    begin -- procedure good_rsv
    dat_s <= x"FF";
    stb_s <= '0';
    tic;
    end procedure init;

    begin -- mk_waves
    init;
    tic;
    tic;
    dat_s <= x"42";
    toggle(stb_s);
    tic;
    dat_s <= x"AA";
    toggle(stb_s);
    tic;
    dat_s <= x"00";
    tic;
    done_s <= true;
    tic;
    tic;
    end process mk_waves;

    -- clock generation
    tb_clk : process is
    constant clk_cy : time := 5 ns;
    begin
    if now < clk_cy then
    rst_s <= '1';
    clk_s <= '0';
    else
    rst_s <= '0';
    clk_s <= '0';
    wait for clk_cy/2;
    clk_s <= '1';
    end if;
    if done_s then wait;
    end if;
    wait for clk_cy/2;
    end process tb_clk;


    end architecture sim;
     
    Mike Treseler, Aug 7, 2004
    #5
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