Reference link
http://home.comcast.net/~mike_treseler/
Q1: Have the single process coding style been synthesized with synopsys tools?
I tried to synthesis the Uart example with Synopsys Design_Analyzer but failure. A error message “ try to use synchronized value”. Dose synopsys not support this coding style or just my tool is too old, 2005 version?
Q2: What does the warning message in Xilinx ise mean?
I synthesized the UART example with ISE7.1 successfully, but a lot of warning messages for variables in design. The warning message is “Potential simulation mismatch, variable ABC declared in block A is assigned in block B”. What is the risk in this warning?
Q3: Does the testbench in reference link work?
I try simulation the Uart example but it wouldn’t run. The error message is “Simulator:222 - Generated C++ compilation was unsuccessful”. Is my ISE7.1 is too old or there is errors in testbench?
Could someone please fix it for ISE7.1?
Q4: Has The Uart example passed post_synthesis simulation?
I wrote a hardware module using single process style. Pre-synthesis behavior simulation is passed. It is synthesized successfully using ISE7.1 with a lot warning as mentioned above. While doing post-synthesis model simulation, “XX” unknown signals are generated inside Hardware module. I do reset the hardware at the beginning of simulation and from waveform reset work. Somehow a few clock cycle after, signal turn to be “XX” unknown.
I use same testbench for pre- and post- synthesis model and the post-synthesis model is generated by ISE7.1, ModuleName_synthesis.vhd.
Has The Uart example done post_synthesis simulation? After all, synthesizable does not mean correctly synthesized.
Thanks for any informantion
http://home.comcast.net/~mike_treseler/
Q1: Have the single process coding style been synthesized with synopsys tools?
I tried to synthesis the Uart example with Synopsys Design_Analyzer but failure. A error message “ try to use synchronized value”. Dose synopsys not support this coding style or just my tool is too old, 2005 version?
Q2: What does the warning message in Xilinx ise mean?
I synthesized the UART example with ISE7.1 successfully, but a lot of warning messages for variables in design. The warning message is “Potential simulation mismatch, variable ABC declared in block A is assigned in block B”. What is the risk in this warning?
Q3: Does the testbench in reference link work?
I try simulation the Uart example but it wouldn’t run. The error message is “Simulator:222 - Generated C++ compilation was unsuccessful”. Is my ISE7.1 is too old or there is errors in testbench?
Could someone please fix it for ISE7.1?
Q4: Has The Uart example passed post_synthesis simulation?
I wrote a hardware module using single process style. Pre-synthesis behavior simulation is passed. It is synthesized successfully using ISE7.1 with a lot warning as mentioned above. While doing post-synthesis model simulation, “XX” unknown signals are generated inside Hardware module. I do reset the hardware at the beginning of simulation and from waveform reset work. Somehow a few clock cycle after, signal turn to be “XX” unknown.
I use same testbench for pre- and post- synthesis model and the post-synthesis model is generated by ISE7.1, ModuleName_synthesis.vhd.
Has The Uart example done post_synthesis simulation? After all, synthesizable does not mean correctly synthesized.
Thanks for any informantion