quetion about verilog code..

Discussion in 'VHDL' started by hsc6320, Nov 26, 2011.

  1. hsc6320

    hsc6320

    Joined:
    Nov 26, 2011
    Messages:
    1
    I'm from korean and i'm a university student in the korea
    I'm 24 years old.. i can't speak english well. i hope you to understand my english skill
    because i have to hurry up this code, i'm writing a this thread

    i'm studying verilog
    but, this code is generated problem
    I can't understand this error....
    I must to complete this code
    please..ㅠㅠ
    I want to your comment

    Error massage is "near ' data_1' : syntax error, unexpected 'IDENTIFIER' "


    module enco (code,code_1, data_1,data_2);
    output [3:0] code;
    output [3:0] code_1;
    input [0:7] data_1;
    input [8:15] data_2;
    reg [3:0] code;
    reg [3:0] code_1;

    always@(data_1)
    begin
    if(data_1[0] == 4'b0000
    data_1[1] == 4'b0010,
    data_1[2] == 4'b0010,
    data_1[3] == 4'b0010,
    data_1[4] == 4'b0010,
    data_1[5] == 4'b0010,
    data_1[6] == 4'b0000,
    data_1[7] == 4'b0000)
    code = 5;
    if(data_1[0] == 4'b0000
    data_1[1] == 4'b0101,
    data_1[2] == 4'b0101,
    data_1[3] == 4'b0111,
    data_1[4] == 4'b0001,
    data_1[5] == 4'b0001,
    data_1[6] == 4'b0000,
    data_1[7] == 4'b0000)
    code = 9;
    if(data_1[0] == 4'b0000
    data_1[1] == 4'b0111,
    data_1[2] == 4'b0100,
    data_1[3] == 4'b0111,
    data_1[4] == 4'b0101,
    data_1[5] == 4'b0111,
    data_1[6] == 4'b0000,
    data_1[7] == 4'b0000)
    code = 12;
    if(data_1[0] == 4'b0000
    data_1[1] == 4'b0111,
    data_1[2] == 4'b0101,
    data_1[3] == 4'b0001,
    data_1[4] == 4'b0001,
    data_1[5] == 4'b0001,
    data_1[6] == 4'b0000,
    data_1[7] == 4'b0000)
    code = 8;

    if(data_1[0] == 4'b0000
    data_1[1] == 4'b0111,
    data_1[2] == 4'b0101,
    data_1[3] == 4'b0111,
    data_1[4] == 4'b0101,
    data_1[5] == 4'b0111,
    data_1[6] == 4'b0000,
    data_1[7] == 4'b0000)
    code = 13; else
    code = 4'b0000;
    end

    always@(data_2)
    begin
    if(data_2[8] == 4'b0000
    data_2[9] == 4'b0010,
    data_2[10] == 4'b0010,
    data_2[11] == 4'b0010,
    data_2[12] == 4'b0010,
    data_2[13] == 4'b0010,
    data_2[14] == 4'b0000,
    data_2[15] == 4'b0000)
    code_1 = 5;
    if(data_2[8] == 4'b0000
    data_2[9] == 4'b0101,
    data_2[10] == 4'b0101,
    data_2[11] == 4'b0111,
    data_2[12] == 4'b0001,
    data_2[13] == 4'b0001,
    data_2[14] == 4'b0000,
    data_2[15] == 4'b0000)
    code_1 = 9;
    if(data_2[8] == 4'b0000
    data_2[9] == 4'b0111,
    data_2[10] == 4'b0100,
    data_2[11] == 4'b0111,
    data_2[12] == 4'b0101,
    data_2[13] == 4'b0111,
    data_2[14] == 4'b0000,
    data_2[15] == 4'b0000)
    code_1 = 12;
    if(data_2[8] == 4'b0000
    data_2[9] == 4'b0111,
    data_2[10] == 4'b0101,
    data_2[11] == 4'b0001,
    data_2[12] == 4'b0001,
    data_2[13] == 4'b0001,
    data_2[14] == 4'b0000,
    data_2[15] == 4'b0000)
    code_1 = 8;

    if(data_2[8] == 4'b0000
    data_2[9] == 4'b0111,
    data_2[10] == 4'b0101,
    data_2[11] == 4'b0111,
    data_2[12] == 4'b0101,
    data_2[13] == 4'b0111,
    data_2[14] == 4'b0000,
    data_2[15] == 4'b0000)
    code_1 = 13; else
    code_1 = 4'b0000;
    end
    endmodule
     
    hsc6320, Nov 26, 2011
    #1
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