quwstion from newbie

Discussion in 'VHDL' started by mobi999, May 22, 2007.

  1. mobi999

    mobi999

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    Hi!
    can u explain what this line do

    result <= ('0' & A)+('0' & B);

    esp this '0' thing

    thanks


    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;

    --------------------------------------------------------

    entity ADDER is

    generic(n: natural :=2);
    port( A: in std_logic_vector(n-1 downto 0);
    B: in std_logic_vector(n-1 downto 0);
    carry: out std_logic;
    sum: out std_logic_vector(n-1 downto 0)
    );

    end ADDER;

    --------------------------------------------------------

    architecture behv of ADDER is

    -- define a temparary signal to store the result

    signal result: std_logic_vector(n downto 0);

    begin

    -- the 3rd bit should be carry

    result <= ('0' & A)+('0' & B);
    sum <= result(n-1 downto 0);
    carry <= result(n);

    end behv;
     
    mobi999, May 22, 2007
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  2. mobi999

    Paxwell

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    Since the answer is one bit more than the inputs. If the '0' wouldn´t be there the carry would be lost. You can´t add two vectors of size x and get a result of size x+1. So the two input vectors have to extended with the most significant bit.
    The vectors are unsigned, that´s important. If a and b are signed it should be a(MSB) & a + b(MSB) & b.

    I hope this explains some.
     
    Last edited: May 22, 2007
    Paxwell, May 22, 2007
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