RAM with Fault model

Discussion in 'VHDL' started by o.tamimi@hotmail.co.uk, Jun 25, 2008.

  1. Guest

    i would appreciate someone's help

    i have to design a VHDL model describing RAM with two different fault
    models, such as stuck at fault and coupling fault
    the following code is for genric RAM model, i do not know how can i
    optimise it so that a functional fault is injected
    library ieee;
    use ieee.std_logic_1164.all;


    entity RAM8X8 is
    port ( Address : in integer range 0 to 7;
    Data : inout std_logic_vector (7 downto 0);
    WE : in std_logic;
    OE : in std_logic);
    CS : in std_logic);


    Architecture behaviour of SRAM8X8 is

    Type RAM8X8_array is array (0 to 7) of std_logic_vector (7 downto
    0);

    Begin
    Process (address,Data,WE,OE,CS ) is
    Variable mem: RAM8X8_array;

    Begin
    Data<= (others => ‘Z’);
    if CS=’0’ then
    if OE=’0’ then
    Data <= mem(Address);
    Elseif WE=’0’ then
    Mem(address):= Data;
    End if;
    End if;
    End process;
    End RAM8X8;

    Many Thanks
    Allan
    , Jun 25, 2008
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Robert Posey
    Replies:
    0
    Views:
    669
    Robert Posey
    Nov 26, 2003
  2. ashu
    Replies:
    1
    Views:
    454
  3. ashu
    Replies:
    2
    Views:
    608
    mysticlol
    Nov 6, 2006
  4. Xin Xiao

    Block RAM Distributed RAM

    Xin Xiao, Jan 7, 2008, in forum: VHDL
    Replies:
    8
    Views:
    1,464
    Duane Clark
    Jan 7, 2008
  5. Replies:
    2
    Views:
    491
    Marcus Harnisch
    Jun 30, 2008
Loading...

Share This Page