RAM with Fault model

Discussion in 'VHDL' started by o.tamimi@hotmail.co.uk, Jun 25, 2008.

  1. Guest

    i would appreciate someone's help

    i have to design a VHDL model describing RAM with two different fault
    models, such as stuck at fault and coupling fault
    the following code is for genric RAM model, i do not know how can i
    optimise it so that a functional fault is injected
    library ieee;
    use ieee.std_logic_1164.all;


    entity RAM8X8 is
    port ( Address : in integer range 0 to 7;
    Data : inout std_logic_vector (7 downto 0);
    WE : in std_logic;
    OE : in std_logic);
    CS : in std_logic);


    Architecture behaviour of SRAM8X8 is

    Type RAM8X8_array is array (0 to 7) of std_logic_vector (7 downto
    0);

    Begin
    Process (address,Data,WE,OE,CS ) is
    Variable mem: RAM8X8_array;

    Begin
    Data<= (others => ‘Z’);
    if CS=’0’ then
    if OE=’0’ then
    Data <= mem(Address);
    Elseif WE=’0’ then
    Mem(address):= Data;
    End if;
    End if;
    End process;
    End RAM8X8;

    Many Thanks
    Allan
    , Jun 25, 2008
    #1
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  2. KJ Guest

    On Jun 24, 8:06 pm, wrote:
    > i would appreciate someone's help
    >
    > i have to design a VHDL  model describing RAM with two different fault
    > models, such as stuck at fault and coupling fault
    > the following code is for genric RAM model, i do not know how can i
    > optimise it so that a functional fault is injected


    Adding Data(0) <= '0'; at the end of your process creates a stuck at
    '0' model.

    Add a new variable called 'Address_faulty' like the following will
    create another stuck at '0' model.
    address_faulty := address - (address mod 2);
    replace Mem(address) with Mem(address_faulty);

    KJ
    KJ, Jun 25, 2008
    #2
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  3. Hi Allan

    writes:
    > i have to design a VHDL model describing RAM with two different fault
    > models, such as stuck at fault and coupling fault


    Since you care about static faults only, I would generate them as part
    of the write action. Although generating the error on read has the nice
    side effect that you can tell what should have been returned. OTOH,
    this violates the rule that checkers should be separated from models...

    BTW: There are three different coupling faults. Check which type you
    are supposed to implement.

    Regards
    Marcus

    --
    note that "property" can also be used as syntaxtic sugar to reference
    a property, breaking the clean design of verilog; [...]

    (seen on http://www.veripool.com/verilog-mode_news.html)
    Marcus Harnisch, Jun 30, 2008
    #3
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