Random Number Generation

Discussion in 'VHDL' started by dpi, Mar 13, 2006.

  1. dpi

    dpi Guest

    Hello,

    I am using the UNIFORM function <UNIFORM(seed1, seed2, rand)> in my
    VHDL code to generate random numbers.

    Whether the seed are initialised to a particular number or left
    uninitialised, for both cases, same sequence of random number are
    generated every time I restart the simulation.

    I suppose if I could start from an unknown, random state (generate a
    random seed at the start of simulation), I could avoid this repetition
    problem. In other languages, I have seen time of the day (which is
    w.r.t. some date in the past) being used for this purpose. Do you know
    how I could do it in VHDL??

    Thanks in advance.
    dpi, Mar 13, 2006
    #1
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  2. dpi wrote:

    > I am using the UNIFORM function <UNIFORM(seed1, seed2, rand)> in my
    > VHDL code to generate random numbers.
    > Whether the seed are initialised to a particular number or left
    > uninitialised, for both cases, same sequence of random number are
    > generated every time I restart the simulation.


    Yes, that's how it works.

    > I suppose if I could start from an unknown, random state (generate a
    > random seed at the start of simulation), I could avoid this repetition
    > problem. In other languages, I have seen time of the day (which is
    > w.r.t. some date in the past) being used for this purpose. Do you know
    > how I could do it in VHDL??


    Your vhdl testbench read the last seed values from a file,
    then calculate and save different values.

    -- Mike Treseler
    Mike Treseler, Mar 13, 2006
    #2
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  3. dpi

    Amal Guest

    If you are using Modelsim, you can use the TCL build-in command rand()
    to get a random number and use it as the seed. Or use [clock second]
    or your own function to get a seed and pass it as a generic to your
    VHDL.

    quietly set seed1 [expr {int(1 + 2147483562*rand())}]; # [1,
    2147483562]
    quietly set seed2 [expr {int(1 + 2147483398*rand())}]; # [1,
    2147483398]

    quietly set options ""

    eval vsim $options -GgSEED1=$seed1 -GgSEED2=$seed2
    ClockErrorCorrection_tb

    -- Amal
    Amal, Mar 13, 2006
    #3
  4. dpi

    Amal Guest

    If you are using Modelsim, you can use the TCL build-in command rand()
    to get a random number and use it as the seed. Or use [clock second]
    or your own function to get a seed and pass it as a generic to your
    VHDL.

    quietly set seed1 [expr {int(1 + 2147483562*rand())}]; # [1,
    2147483562]
    quietly set seed2 [expr {int(1 + 2147483398*rand())}]; # [1,
    2147483398]

    quietly set options ""

    eval vsim $options -GgSEED1=$seed1 -GgSEED2=$seed2 top_tb

    -- Amal
    Amal, Mar 13, 2006
    #4
  5. dpi

    vipinlal

    Joined:
    Feb 25, 2010
    Messages:
    38
    The package you are using is not synthesizable.you can use this code instead:
    vhdlguru.blogspot.com/2010/03/random-number-generator-in-vhdl.html
    vipinlal, Mar 26, 2010
    #5
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