Random Number Generator??

Discussion in 'VHDL' started by Kingsley Oteng, Apr 27, 2004.

  1. Does VHDL have a random number generator built in it? Something like the RND
    command in C++?? I have a system whose performance I would like to test by
    getting it to randomly generate inputs...problem is I don't know how to
    randomly generate numbers....

    - Kingsley
     
    Kingsley Oteng, Apr 27, 2004
    #1
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  2. Kingsley Oteng <> wrote:
    > Does VHDL have a random number generator built in it? Something like the RND
    > command in C++?? I have a system whose performance I would like to test by
    > getting it to randomly generate inputs...problem is I don't know how to
    > randomly generate numbers....
    >
    > - Kingsley
    >
    >

    How about a chain of FF with mod2 adders?
    --
    Wing Wong.
     
    Wing Fong Wong, Apr 28, 2004
    #2
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  3. Kingsley Oteng

    Ronald Hecht Guest

    Have a look at

    http://verificationguild.com/modules.php?name=Downloads&d_op=viewdownload&cid=3

    Ronald

    Kingsley Oteng wrote:
    > Does VHDL have a random number generator built in it? Something like the RND
    > command in C++?? I have a system whose performance I would like to test by
    > getting it to randomly generate inputs...problem is I don't know how to
    > randomly generate numbers....
    >
    > - Kingsley
    >
    >
     
    Ronald Hecht, Apr 28, 2004
    #3
  4. On Wed, 28 Apr 2004 08:34:14 +1000, "Kingsley Oteng"
    <> wrote:

    >Does VHDL have a random number generator built in it? Something like the RND
    >command in C++?? I have a system whose performance I would like to test by
    >getting it to randomly generate inputs...problem is I don't know how to
    >randomly generate numbers....


    VHDL has an excellent built-in random number generator, if you count
    the IEEE.math_real package as "built-in". It's called UNIFORM.
    You need to keep two seed values (of type POSITIVE) on its behalf.
    Every time you invoke it, it updates your seed values and gives you
    a random REAL value in the range 0 to (not quite) 1.0. You can
    then massage this REAL value any way you want to get your random
    bit pattern or whatever.

    library ieee;
    use ieee.math_real.all; -- for UNIFORM, TRUNC
    use ieee.numeric_std.all; -- for TO_UNSIGNED
    ....

    process
    -- Seed values for random generator
    variable seed1, seed2: positive;
    -- Random real-number value in range 0 to 1.0
    variable rand: real;
    -- Random integer value in range 0..4095
    variable int_rand: integer;
    -- Random 12-bit stimulus
    variable stim: std_logic_vector(11 downto 0);
    begin
    -- initialise seed1, seed2 if you want -
    -- otherwise they're initialised to 1 by default
    loop -- testbench stimulus loop?
    UNIFORM(seed1, seed2, rand);
    -- get a 12-bit random value...
    -- 1. rescale to 0..(nearly)4096, find integer part
    int_rand := INTEGER(TRUNC(rand*4096.0));
    -- 2. convert to std_logic_vector
    stim := std_logic_vector(to_unsigned(int_rand, stim'LENGTH));
    ...

    Modify according to taste.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, Apr 28, 2004
    #4
  5. Jonathan Bromley a écrit:

    > VHDL has an excellent built-in random number generator, if you count
    > the IEEE.math_real package as "built-in". It's called UNIFORM.
    > You need to keep two seed values (of type POSITIVE) on its behalf.
    > Every time you invoke it, it updates your seed values and gives you
    > a random REAL value in the range 0 to (not quite) 1.0. You can
    > then massage this REAL value any way you want to get your random
    > bit pattern or whatever.


    Great!
    I was just about to ask some help about the uniform procedure (I came up
    with a nice random jitter generator last week but my use of uniform is a
    bit uncertain). Your post answers everything I wanted to ask, thanks a
    lot :eek:)

    --
    ____ _ __ ___
    | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
    | | | | | (_| |_| | Invalid return address: remove the -
    |_| |_|_|\__|\___/
     
    Nicolas Matringe, Apr 28, 2004
    #5
  6. Kingsley Oteng

    AbouHimed Guest

    Thanks for the informations, but does anyone know how to get the
    IEEE.math_real library...?

    Thanks again..
     
    AbouHimed, May 21, 2004
    #6
  7. Kingsley Oteng

    AbouHimed Guest

    Does anyone know where can I get the IEEE.math_real library?

    Looking forward to hear from you,

    AbouHimed
     
    AbouHimed, May 21, 2004
    #7
  8. On Fri, 21 May 2004 00:11:56 -0400, "AbouHimed"
    <> wrote:

    >Thanks for the informations, but does anyone know how to get the
    >IEEE.math_real library...?


    It's distributed with your simulator, unless you have a truly
    bizarre simulator.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, May 21, 2004
    #8
  9. Kingsley Oteng

    obaskirt

    Joined:
    Sep 18, 2007
    Messages:
    2
    obaskirt, Sep 19, 2007
    #9
  10. Kingsley Oteng

    ctbram

    Joined:
    Mar 1, 2009
    Messages:
    1
    use of ieee.math_real in quartus II

    Can someone please for the love of god post a simple example of how to implement this psuedo random number generator using the ieee.math_real library uniform funtion??????!!!!!!!????????!!!!!!!!

    I am on the verge of a nervous break down. I have found several "kinda sorta" examples and in every case when I try to implement/synthesize these the quartus compiler vomits all over bitching that

    Error (10414): VHDL Unsupported Feature error at psuedo_random_number.vhd(22): cannot synthesize non-constant real objects or values

    I just want to do something like this.

    set up a seed, generate psuedo random numbers on rising edge of clk, when the user presses a button grab the current value! Why do I feel like I have to have mulitple phd's in advanced interdemensional quantum quaszy nondeterministic nonnewtonian theoretic physics th get this to work!!!!!

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use ieee.math_real.all;

    entity psuedo_random_number is
    port(
    ld : in std_logic;
    clk : in std_logic;
    result : out std_logic_vector(7 downto 0)
    );
    end entity psuedo_random_number;

    architecture psuedo_random_number of psuedo_random_number is


    begin

    process(clk, ld)
    variable s1 : positive := 234; -- Set to some seed value
    variable s2 : positive := 567; -- Set to some seed value
    variable randNum : real; -- Where the random number will be set
    variable slv : std_logic_vector(7 downto 0);
    begin
    uniform(s1, s2, randNum); -- Sets randNum to a value between 0.0 and under 1.0

    randNum := randNum * 10.0; -- randNum has a value between 0.0 and under 10
    randNum := floor(randNum) + 3.0; -- randnum has a value between 3.0 and 12.0 (without fraction)
    slv := std_logic_vector(to_unsigned(integer(randNum), 8)); -- Convert to std_logic_vector

    if clk'event and clk = '1' and ld = '0' then
    result <= slv;
    end if;
    -- All in one line
    --slv := std_logic_vector(to_unsigned(integer(floor(randnum * 256.0)), 8)); -- random data
    end process;

    end architecture psuedo_random_number;
     
    ctbram, Mar 1, 2009
    #10
  11. Kingsley Oteng

    vipinlal

    Joined:
    Feb 25, 2010
    Messages:
    38
    there is no built in function in VHDL for random number generation..
    here is a code available which is also synthesizable..
    vhdlguru.blogspot.com/2010/03/random-number-generator-in-vhdl.html
     
    vipinlal, Mar 26, 2010
    #11
  12. Kingsley Oteng

    rahul.iyer

    Joined:
    Aug 9, 2010
    Messages:
    1
    The below code generates the random number generator

    function random (
    data_width : positive := 27;
    seed1 : positive := 1;
    seed2 : positive := 1
    ) return std_logic_vector is
    variable real_random : real := 0.0;
    variable s1 : positive := 1;
    variable s2 : positive := 1;
    variable i : integer := 0;
    variable j : integer := 0;
    variable random_number : std_logic_vector(data_width-1 downto 0);
    constant max_natural : natural range 30 downto 1 := 30;
    begin
    s1 := seed1;
    s2 := seed2;
    while ((i+30) < data_width) loop
    j := i+30;
    uniform(s1, s2, real_random);
    random_number(j downto i) :=
    std_logic_vector(to_unsigned(integer((trunc(real_random*((2**max_natural-1)*1.0)))),max_natural+1));
    i := i + 31;
    end loop;
    s2 := seed2 + i;
    uniform(s1, s2, real_random);
    random_number(data_width-1 downto i) :=
    std_logic_vector(to_unsigned(integer((trunc(real_random*((2**max_natural-1)*1.0)))),data_width-i));
    return random_number;
    end function random;
     
    rahul.iyer, Aug 9, 2010
    #12
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