>Does VHDL have a random number generator built in it? Something like the RND
command in C++?? I have a system whose performance I would like to test by
getting it to randomly generate inputs...problem is I don't know how to
randomly generate numbers....
VHDL has an excellent built-in random number generator, if you count
the IEEE.math_real package as "built-in". It's called UNIFORM.
You need to keep two seed values (of type POSITIVE) on its behalf.
Every time you invoke it, it updates your seed values and gives you
a random REAL value in the range 0 to (not quite) 1.0. You can
then massage this REAL value any way you want to get your random
bit pattern or whatever.
library ieee;
use ieee.math_real.all; -- for UNIFORM, TRUNC
use ieee.numeric_std.all; -- for TO_UNSIGNED
....
process
-- Seed values for random generator
variable seed1, seed2: positive;
-- Random real-number value in range 0 to 1.0
variable rand: real;
-- Random integer value in range 0..4095
variable int_rand: integer;
-- Random 12-bit stimulus
variable stim: std_logic_vector(11 downto 0);
begin
-- initialise seed1, seed2 if you want -
-- otherwise they're initialised to 1 by default
loop -- testbench stimulus loop?
UNIFORM(seed1, seed2, rand);
-- get a 12-bit random value...
-- 1. rescale to 0..(nearly)4096, find integer part
int_rand := INTEGER(TRUNC(rand*4096.0));
-- 2. convert to std_logic_vector
stim := std_logic_vector(to_unsigned(int_rand, stim'LENGTH));
...
Modify according to taste.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
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