Random Value for LFSR (just simulation)

Discussion in 'VHDL' started by Martin, Feb 17, 2009.

  1. Martin

    Martin Guest

    Hi

    I have a very simple LFSR in my design that looks as follows:

    architecture Behavior of PRNG is
    signal temp : std_logic_vector(7 downto 0) := B"01110101";

    begin
    process(clk)
    begin
    if ( clk'event and clk='1' ) then
    temp <= (temp(1) xor temp(0)) & temp(7 downto 1);
    PRNG_OUT <= temp;
    end if;
    end process;
    end architecture Behavior;

    The problem that I have here now is obviously that I have the same
    seed for each startup of
    the simulation! I wonder if there is a very easy way to get 8 random
    bits for my temp signal
    at the beginning? When checking google the most things I found was
    making use of some
    random sources from the hardware with oscis and so on but in my case I
    just need it for simulation!

    Many thanks!
    Martin, Feb 17, 2009
    #1
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  2. Martin

    Tricky Guest

    On 17 Feb, 15:31, Martin <> wrote:
    > Hi
    >
    > I have a very simple LFSR in my design that looks as follows:
    >
    > architecture Behavior of PRNG is
    >   signal temp : std_logic_vector(7 downto 0) := B"01110101";
    >
    >   begin
    >   process(clk)
    >   begin
    >          if ( clk'event and clk='1' ) then
    >                 temp      <= (temp(1) xor temp(0)) & temp(7 downto 1);
    >                 PRNG_OUT  <= temp;
    >           end if;
    >   end process;
    > end architecture Behavior;
    >
    > The problem that I have here now is obviously that I have the same
    > seed for each startup of
    > the simulation! I wonder if there is a very easy way to get 8 random
    > bits for my temp signal
    > at the beginning? When checking google the most things I found was
    > making use of some
    > random sources from the hardware with oscis and so on but in my case I
    > just need it for simulation!
    >
    > Many thanks!


    Unfortunatly there is no way of getting hold of anything that changes
    (like system time) in VHDL. You would have the same problems if you
    used the uniform function (generates random reals between 0 and 1)
    from the ieee.math_real package too (although this is useful for re-
    running input vector sequences).

    The only solution I have heard of is to set up a generic in the
    testbench as the seed value that is then set via a TCL script when you
    run the testbench.
    Tricky, Feb 17, 2009
    #2
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  3. Martin

    Guest

    On Feb 17, 10:45 am, Tricky <> wrote:
    > On 17 Feb, 15:31, Martin <> wrote:
    >
    >
    >
    > > Hi

    >
    > > I have a very simple LFSR in my design that looks as follows:

    >
    > > architecture Behavior of PRNG is
    > >   signal temp : std_logic_vector(7 downto 0) := B"01110101";

    >
    > >   begin
    > >   process(clk)
    > >   begin
    > >          if ( clk'event and clk='1' ) then
    > >                 temp      <= (temp(1) xor temp(0)) & temp(7 downto 1);
    > >                 PRNG_OUT  <= temp;
    > >           end if;
    > >   end process;
    > > end architecture Behavior;

    >
    > > The problem that I have here now is obviously that I have the same
    > > seed for each startup of
    > > the simulation! I wonder if there is a very easy way to get 8 random
    > > bits for my temp signal
    > > at the beginning? When checking google the most things I found was
    > > making use of some
    > > random sources from the hardware with oscis and so on but in my case I
    > > just need it for simulation!

    >
    > > Many thanks!

    >
    > Unfortunatly there is no way of getting hold of anything that changes
    > (like system time) in VHDL. You would have the same problems if you
    > used the uniform function (generates random reals between 0 and 1)
    > from the ieee.math_real package too (although this is useful for re-
    > running input vector sequences).
    >
    > The only solution I have heard of is to set up a generic in the
    > testbench as the seed value that is then set via a TCL script when you
    > run the testbench.


    How about (if you're running *nix operating system), reading from and
    parsing one of the special files (somewhere in dev/* or proc/*) that
    might get changed on the fly?

    - Kenn
    , Feb 17, 2009
    #3
  4. Martin <> writes:

    > The problem that I have here now is obviously that I have the same
    > seed for each startup of the simulation! I wonder if there is a very
    > easy way to get 8 random bits for my temp signal at the beginning?


    You seem to mix up two issues:

    1. You want to change the seed: Valid requirement. Pseudo random
    number sequences get kind of boring after a while. Other have
    posted solutions. I prefer using generics for that kind of stuff.

    2. You want a random seed. Do you really? Think about it. What if you
    find a bug and now want to verify your fix. Will you be able to
    reproduce the exact system state?

    I would use reproducible generated numbers, perhaps the output from
    $(date +%s). Store that number along with your simulation data.

    Regards
    Marcus

    --
    note that "property" can also be used as syntaxtic sugar to reference
    a property, breaking the clean design of verilog; [...]

    (seen on http://www.veripool.com/verilog-mode_news.html)
    Marcus Harnisch, Feb 18, 2009
    #4
  5. Martin

    whygee Guest

    Martin wrote:
    > Hi

    <snip>

    > The problem that I have here now is obviously that I have the same
    > seed for each startup of
    > the simulation! I wonder if there is a very easy way to get 8 random
    > bits for my temp signal
    > at the beginning? When checking google the most things I found was
    > making use of some
    > random sources from the hardware with oscis and so on but in my case I
    > just need it for simulation!


    back in 2001 we had the same requirements for the design of F-CPU,
    you'll find the solution in http://f-cpu.seul.org/whygee/pres-isima/snapshot_yg_29_07_2002.tbz
    in the f-cpu/vhdl/common directory of the archive.

    for clarity, i have put the 2 relevant files at
    http://yasep.org/~whygee/random.txt
    http://yasep.org/~whygee/random_simple.vhdl
    This version gets data from a file,
    which is /dev/urandom in this case.
    If you want to input from a regular file,
    i'll have to search an earlier version
    that properly handles wrap-around at
    the end of the input file...

    > Many thanks!

    enjoy and adapt,
    yg

    --
    http://ygdes.com / http://yasep.org
    whygee, Feb 19, 2009
    #5
  6. Martin

    David Binnie Guest

    If you are actually going to implement this you can count the phase
    difference between a dividend of the board clock (chip oscilator) and an
    FPGA generated clock (ring oscilator) of the same approximate frequency, to
    generate a random seed.

    Dr B
    David Binnie, Feb 28, 2009
    #6
  7. Martin

    Guest

    Just a little warning: you'll need 3 taps to get a maximum length 8-
    bit sequence.
    , Mar 2, 2009
    #7
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