RC4 - someone help pleas!!

Discussion in 'VHDL' started by Ahmed Samieh, Jun 9, 2007.

  1. Ahmed Samieh

    Ahmed Samieh Guest

    Hi all,

    i'm tring to implement RC4 algorithm on fpga, i wrote the vhdl code
    and simulation work fine too
    but when i want to synthesize the errors and warnings pops up in my
    face :(

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.numeric_std.all;
    --
    ENTITY RC4 IS
    GENERIC (d_width : natural := 8;
    a_width : natural := 8);
    PORT(clk : IN std_logic;
    data_en : IN std_logic;
    seed : IN std_logic_vector(63 DOWNTO 0) :=
    X"0369CF258BE147AD";
    data_out : OUT std_logic_vector(d_width-1 DOWNTO 0));
    END ENTITY RC4;
    --
    ARCHITECTURE Arch OF RC4 IS
    SUBTYPE byte IS natural RANGE 0 TO 2**d_width-1;
    TYPE ram IS ARRAY (natural RANGE <>) OF byte;
    SIGNAL x_s,y_s : byte;
    SIGNAL rst_1_s,rst_2_s : std_logic := '0';
    BEGIN
    rise : PROCESS(clk,data_en,seed,rst_1_s,rst_2_s)
    VARIABLE temp_1_v,temp_2_v,temp_3_v : byte;
    VARIABLE state_v : ram(0 TO 2**a_width-1);
    VARIABLE j_v,x_v,y_v : byte;
    VARIABLE seed_v : ram(0 TO 7);
    -- ATTRIBUTE logic_block : boolean;
    -- ATTRIBUTE logic_block OF state_v: VARIABLE IS true;
    BEGIN
    IF (rst_1_s = rst_2_s) THEN
    FOR i IN 7 DOWNTO 0 LOOP
    seed_v(i) := to_integer( unsigned( seed((i+1)*8-1 DOWNTO
    i*8) ) );
    END LOOP;
    FOR i IN 0 TO 2**a_width-1 LOOP
    state_v(i) := i;
    END LOOP;
    FOR i IN 0 TO 2**a_width-1 LOOP
    temp_1_v := seed_v(i mod 8);
    temp_2_v := state_v(i);
    j_v := (temp_1_v + temp_2_v + j_v) mod 2**a_width;
    temp_3_v := state_v(j_v);
    state_v(i) := temp_3_v;
    state_v(j_v) := temp_2_v;
    END LOOP;
    x_s <= 0;
    y_s <= 0;
    rst_1_s <= NOT(rst_2_s);
    data_out <= (OTHERS => '0');
    ELSIF rising_edge(clk) THEN
    IF (data_en = '1') THEN
    x_v := (x_s + 1) mod 2**a_width;
    y_v := (y_s + state_v(x_v)) mod 2**a_width;
    temp_1_v := state_v(x_v);
    temp_2_v := state_v(y_v);
    state_v(x_v) := temp_2_v;
    state_v(y_v) := temp_1_v;
    temp_3_v := state_v((temp_1_v + temp_2_v) mod 2**a_width);
    data_out <= std_logic_vector(to_unsigned(temp_3_v, d_width));
    x_s <= x_v;
    y_s <= y_v;
    END IF;
    END IF;
    END PROCESS rise;
    new_frame_reset : PROCESS(data_en,rst_1_s)
    BEGIN
    IF rising_edge(data_en) THEN
    rst_2_s <= rst_1_s;
    END IF;
    END PROCESS new_frame_reset;
    END ARCHITECTURE Arch;

    thanx,

    Ahmed Samieh
    Ahmed Samieh, Jun 9, 2007
    #1
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  2. Ahmed Samieh

    Ahmed Samieh Guest

    On Jun 9, 11:29 pm, Ahmed Samieh <> wrote:
    > Hi all,


    1st problem come from

    > FOR i IN 0 TO 2**a_width-1 LOOP
    > state_v(i) := i;
    > END LOOP;


    where state_v is 256*8 ram (array of 256 bytes)

    but i don't understand why i got such a warning

    Warning: 5783: Module WiFi_MAC.Test(Arch){generic map (d_width => 8
    a_width => 8)}, Net rst_1_s: This signal has multiple drivers. This
    may lead to simulation mismatch.

    ???

    any suggestions?

    thanx,

    Ahmed Samieh
    Ahmed Samieh, Jun 10, 2007
    #2
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  3. "Ahmed Samieh" <> wrote in message
    news:...
    > On Jun 9, 11:29 pm, Ahmed Samieh <> wrote:
    >> Hi all,

    >
    > 1st problem come from
    >
    >> FOR i IN 0 TO 2**a_width-1 LOOP
    >> state_v(i) := i;
    >> END LOOP;

    >
    > where state_v is 256*8 ram (array of 256 bytes)
    >
    > but i don't understand why i got such a warning
    >
    > Warning: 5783: Module WiFi_MAC.Test(Arch){generic map (d_width => 8
    > a_width => 8)}, Net rst_1_s: This signal has multiple drivers. This
    > may lead to simulation mismatch.


    The warning is complaining about the signal rst_1_s. You are assigning to it
    twice, and that leads to "multiple drivers".

    -Michael.
    Michael Jørgensen, Jun 11, 2007
    #3
  4. Ahmed Samieh

    Ahmed Samieh Guest

    On Jun 11, 2:00 pm, "Michael Jørgensen" <> wrote:
    > "Ahmed Samieh" <> wrote in message
    >
    > news:...
    >
    >
    >
    >
    >
    > > On Jun 9, 11:29 pm, Ahmed Samieh <> wrote:
    > >> Hi all,

    >
    > > 1st problem come from

    >
    > >> FOR i IN 0 TO 2**a_width-1 LOOP
    > >> state_v(i) := i;
    > >> END LOOP;

    >
    > > where state_v is 256*8 ram (array of 256 bytes)

    >
    > > but i don't understand why i got such a warning

    >
    > > Warning: 5783: Module WiFi_MAC.Test(Arch){generic map (d_width => 8
    > > a_width => 8)}, Net rst_1_s: This signal has multiple drivers. This
    > > may lead to simulation mismatch.

    >
    > The warning is complaining about the signal rst_1_s. You are assigning to it
    > twice, and that leads to "multiple drivers".
    >
    > -Michael.- Hide quoted text -
    >
    > - Show quoted text -


    thanx Michael,

    but if you talk a look in the code you will find only one driver for
    rst_1_s
    only
    > rst_1_s <= NOT(rst_2_s);


    so what is wrong with this code ?

    Ahmed Samieh
    Ahmed Samieh, Jun 15, 2007
    #4
  5. On Fri, 15 Jun 2007 15:54:12 -0700, Ahmed Samieh <>
    wrote:

    >> > Warning: 5783: Module WiFi_MAC.Test(Arch){generic map (d_width => 8
    >> > a_width => 8)}, Net rst_1_s: This signal has multiple drivers. This
    >> > may lead to simulation mismatch.

    >>
    >> The warning is complaining about the signal rst_1_s. You are assigning to it
    >> twice, and that leads to "multiple drivers".


    >thanx Michael,


    >but if you talk a look in the code you will find only one driver for
    >rst_1_s


    >> rst_1_s <= NOT(rst_2_s);

    and
    SIGNAL rst_1_s,rst_2_s : std_logic := '0';

    Make that two.

    - Brian
    Brian Drummond, Jun 16, 2007
    #5
  6. Ahmed Samieh

    Ahmed Samieh Guest

    On Jun 16, 4:22 pm, Brian Drummond <>
    wrote:
    > >> rst_1_s <= NOT(rst_2_s);

    >
    > and
    > SIGNAL rst_1_s,rst_2_s : std_logic := '0';
    >
    > Make that two.
    >
    > - Brian


    it is only an initial value to the signal not signal driver, so there
    is no repot about rst_2_s

    Ahmed Samieh
    Ahmed Samieh, Jun 17, 2007
    #6
  7. Ahmed Samieh

    Evan Lavelle Guest

    On Sun, 17 Jun 2007 04:47:03 -0700, Ahmed Samieh <>
    wrote:

    >On Jun 16, 4:22 pm, Brian Drummond <>
    >wrote:
    >> >> rst_1_s <= NOT(rst_2_s);

    >>
    >> and
    >> SIGNAL rst_1_s,rst_2_s : std_logic := '0';
    >>
    >> Make that two.
    >>
    >> - Brian

    >
    >it is only an initial value to the signal not signal driver, so there
    >is no repot about rst_2_s


    You're right, it's just a default value; this doesn't create a driver.
    A signal always has a default value; you've just specified an explicit
    one here, rather than using the 'implicit default' (in Verilog,
    though, initialisation is just a shorthand for a continuous
    assignment, so this *would* be a problem).

    I think your problem is simply that your code is unsynthesisable, and
    your tool is just trying (unsuccessfully) to tell you that. rst_1_s is
    part of a combinatorial feedback loop (look at 'rst_1_s = rst_2_s' and
    'rst_1_s <= not(rst_2_s'), *and* you're trying to give it a default
    value. You need to sketch out what hardware you're trying to build,
    and then try to code up that hardware, using some combination of
    clocked and combinatorial processes.

    Evan
    Evan Lavelle, Jun 18, 2007
    #7
  8. Ahmed Samieh

    Evan Lavelle Guest

    On Mon, 18 Jun 2007 09:57:18 +0100, Evan Lavelle <>
    wrote:


    >(in Verilog,
    >though, initialisation is just a shorthand for a continuous
    >assignment, so this *would* be a problem).


    Technically, that should have been 'a blocking assignment in an
    initial construct', rather than 'a continuous assignment'.

    Evan
    Evan Lavelle, Jun 18, 2007
    #8
  9. Ahmed Samieh

    Ahmed Samieh Guest

    On Jun 18, 11:57 am, Evan Lavelle <> wrote:
    > I think your problem is simply that your code is unsynthesisable, and
    > your tool is just trying (unsuccessfully) to tell you that. rst_1_s is
    > part of a combinatorial feedback loop (look at 'rst_1_s = rst_2_s' and
    > 'rst_1_s <= not(rst_2_s'), *and* you're trying to give it a default
    > value. You need to sketch out what hardware you're trying to build,
    > and then try to code up that hardware, using some combination of
    > clocked and combinatorial processes.
    >
    > Evan


    thanx Evan,

    ok..the problem in the code and the point which can't be done within
    the code is :
    i need to access 256 location using loop - only during one clock !!!

    Ahmed Samieh
    Ahmed Samieh, Jun 18, 2007
    #9
  10. Hey Ahmed,

    I think you have several problems in your code. But I don't agree that
    writing to 256 location in one cycle would be a problem, provided you don't
    want a RAM. Obviously if you want to write to a RAM you need to do it line
    by line etc.

    Ok, to cut a long story short. The problem appears to come from two things:

    firstly you make signals rst_1_s and rst_2_s and init them to '0'. be
    cautious here, this won't simulate the same as it runs...

    secondly, you've some crazy combinational logic with the two reset signals
    and data_en. At the very least this _must_ make a latch for rst_1_s
    somewhere.

    Have a look at what you're trying to do, and (as others have already
    suggested) try drawing out the circuit first by hand.

    I also think you're cheating the simulator by including data_en in your
    sensitivity list for 'rise' process.

    to summarise:
    -when data_en has a rising_edge state rst_2_s becomes the same as rst_1_s
    -immediately these are equal, 'rise' executes and sets them inequal through
    a combinational path.
    -so you have a tiny ~ns pulse driving the first part of the 'rise' process
    -BUT you have a clock AND data_en = '1' comparison also in the 'rise'
    process ...

    This is very confusing - how exactly are you trying to do this?? Have
    another look through and post some more code when you make some progress :)

    Ben
    Benjamin Todd, Jun 18, 2007
    #10
  11. Ahmed Samieh

    Evan Lavelle Guest

    On Mon, 18 Jun 2007 07:23:46 -0700, Ahmed Samieh <>
    wrote:

    >On Jun 18, 11:57 am, Evan Lavelle <> wrote:
    >> I think your problem is simply that your code is unsynthesisable, and
    >> your tool is just trying (unsuccessfully) to tell you that. rst_1_s is
    >> part of a combinatorial feedback loop (look at 'rst_1_s = rst_2_s' and
    >> 'rst_1_s <= not(rst_2_s'), *and* you're trying to give it a default
    >> value. You need to sketch out what hardware you're trying to build,
    >> and then try to code up that hardware, using some combination of
    >> clocked and combinatorial processes.
    >>
    >> Evan

    >
    >thanx Evan,
    >
    >ok..the problem in the code and the point which can't be done within
    >the code is :
    >i need to access 256 location using loop - only during one clock !!!


    I haven't looked at your code in detail, but at first sight the loops
    look synthesisable (but will turn into a lot of hardware). The problem
    is more likely to be the combinatorial feedback loop I mentioned
    above. What hardware are you trying to create with rst_1_s/rst_2_s in
    your process "reset" branch? Can you draw a schematic for it?

    Evan
    Evan Lavelle, Jun 18, 2007
    #11
  12. Ahmed Samieh

    Ahmed Samieh Guest

    thanx Benjamin, thanx Even

    ok the problem is that it is a software algorithm basically
    http://en.wikipedia.org/wiki/RC4_(cipher)

    so i have to run the initialization function during rise edge of
    data_en

    for i from 0 to 255
    S := i
    endfor
    j := 0
    for i from 0 to 255
    j := (j + S + key[i mod keylength]) mod 256
    swap(S,S[j])
    endfor
    i := 0
    j := 0

    then for each clock and during data_en = '1' i have to run the prga
    function

    i := (i + 1) mod 256
    j := (j + S) mod 256
    swap(S,S[j])
    output S[(S + S[j]) mod 256]

    that is the algorithm.

    the code in vhdl without any modification , and not free of errors :

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.numeric_std.all;
    --
    ENTITY RC4 IS
    GENERIC (d_width : natural := 8;
    a_width : natural := 8);
    PORT(clk : IN std_logic;
    data_en : IN std_logic;
    seed : IN std_logic_vector(63 DOWNTO 0);
    data_out : OUT std_logic_vector(d_width-1 DOWNTO 0));
    END ENTITY RC4;
    --
    ARCHITECTURE Arch OF RC4 IS
    SUBTYPE byte IS natural RANGE 0 TO 2**d_width-1;
    TYPE ram IS ARRAY (natural RANGE <>) OF byte;
    SIGNAL seed_s : ram(0 TO 7);
    SIGNAL x_s,y_s : byte;
    BEGIN
    seed_convert : PROCESS(seed)
    BEGIN
    FOR i IN 7 DOWNTO 0 LOOP
    seed_s(i) <= to_integer(unsigned(seed((i+1)*8-1 DOWNTO i*8)));
    END LOOP;
    END PROCESS seed_convert;
    --
    main : PROCESS(clk,data_en,seed_s)
    VARIABLE temp_1_v,temp_2_v,temp_3_v : byte;
    VARIABLE state_v : ram(0 TO 2**a_width-1);
    VARIABLE j_v,x_v,y_v : byte;
    BEGIN
    IF rising_edge(data_en) THEN
    FOR i IN 0 TO 2**a_width-1 LOOP
    state_v(i) := i;
    END LOOP;
    j_v := 0;
    FOR i IN 0 TO 2**a_width-1 LOOP
    j_v := (seed_s(i mod 8) + state_v(i) + j_v) mod 2**a_width;
    temp_1_v := state_v(i); -- swap(state_v(i),state(j_v))
    temp_2_v := state_v(j_v); -- swap(state_v(i),state(j_v))
    state_v(i) := temp_1_v; -- swap(state_v(i),state(j_v))
    state_v(j_v) := temp_1_v; -- swap(state_v(i),state(j_v))
    END LOOP;
    x_s <= 0;
    y_s <= 0;
    data_out <= (OTHERS => '0');
    ELSIF rising_edge(clk) THEN
    IF (data_en = '1') THEN
    x_v := (x_s + 1) mod 2**a_width;
    y_v := (y_s + state_v(x_v)) mod 2**a_width;
    temp_1_v := state_v(x_v);
    temp_2_v := state_v(y_v);
    state_v(x_v) := temp_2_v;
    state_v(y_v) := temp_1_v;
    temp_3_v := state_v((temp_1_v + temp_2_v) mod 2**a_width);
    data_out <= std_logic_vector(to_unsigned(temp_3_v, d_width));
    x_s <= x_v;
    y_s <= y_v;
    END IF;
    END IF;
    END PROCESS main;
    END ARCHITECTURE Arch;

    the algorithm is :

    - if rising_edge(data_en) then initialize state
    - elsif rising_edge(clk) and data_en = '1' then prga

    * initialize state
    - state is 256 byte from 0 to 255
    - set state(i) = i;
    then
    using seed, swap state -the algorithm above-
    - now it is ready to prga

    * prga
    for each clock output 1 byte and swap 2 bytes in state

    problems....
    1 - error to drive process with 2 clocks - rising_edge(data_en) and
    rising_edge(clk) -
    2 - i'm tring to access 2 memory locations at the same time for booth
    read and write, and repeat this 256 times only in halve clock (start
    from riseing_edge(data_en) and before rising_edge(clock) - where
    data_en changed with falling_edge(clk) ) .... complex ?? :(

    Ahmed Samieh
    Ahmed Samieh, Jun 19, 2007
    #12
  13. Ahmed Samieh

    Ahmed Samieh Guest

    On Jun 19, 2:50 pm, Ahmed Samieh <> wrote:
    > state_v(i) := temp_1_v; -- swap(state_v(i),state(j_v))


    sorry,
    state_v(i) := temp_2_v; -- swap(state_v(i),state(j_v))

    Ahmed Samieh
    Ahmed Samieh, Jun 19, 2007
    #13
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