Re: 2 inverters in series

Discussion in 'VHDL' started by mike, Apr 5, 2005.

  1. mike

    mike Guest

    Jason Zheng <> wrote in message news:<d2rsvr$ndj$>...
    > wrote:
    > > Hi
    > >
    > > Is there some trick that your can do so that when assigning 2 inverter
    > > in series, that they won't get "optimised" away. I don't know why I
    > > need this, but it would be cool to do. Thanks. I know this not really
    > > about verilog, but it would be great if I can do it using verilog
    > > without using schematics.
    > >

    > For synplify, I think you need to use "syn_keep" directive on the output
    > net to preserve the seemingly redundant logic. There might be use for
    > this on some specialty circuits, such as some interfacing logic between
    > two clock domains. But other than that, I don't know why you would need it.
    >
    > -jz

    regards:

    good post

    thank you
    May goodness be with you all
     
    mike, Apr 5, 2005
    #1
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