Re: Adding reference into a record type

Discussion in 'VHDL' started by KJ, Jul 18, 2008.

  1. KJ

    KJ Guest

    "Tricky" <> wrote in message
    news:...
    > On 17 Jul, 17:27, Tricky <> wrote:
    >> Unfortnalty, Ive just reaslised that the image and dimension types I
    >> have declared are more likely to be than variables,

    >
    > Thats meant to be "more likely to be constants than variables"
    >


    Something that is 'likely to be constant' still sounds like it's a variable
    to me.

    KJ
     
    KJ, Jul 18, 2008
    #1
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