Re: Aligned PLL clocks in RTL simulation

Discussion in 'VHDL' started by Mark McDougall, Nov 17, 2008.

  1. Jonathan Bromley wrote:

    > I swapped-in
    > much simpler, but perfectly adequate in-house models and
    > got x10 simulation speedup.


    Ditto!

    Regards,

    --
    Mark McDougall, Engineer
    Virtual Logic Pty Ltd, <http://www.vl.com.au>
    21-25 King St, Rockdale, 2216
    Ph: +612-9599-3255 Fax: +612-9599-3266
     
    Mark McDougall, Nov 17, 2008
    #1
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