R
Ray Andraka
Yes, we have. One approach we had success with was one that used a DDS type
setup where the increment value got bumped up/down depending on the phase of the
accumulator vs the reference. Works quite well as long as the reference is
fairly stable. In our case we needed to track a mechanical system which had a
fairly high variance on the reference, so we wound up putting a lot of extra
crap on the design to improve the transient response without it going into
oscillation. Still lots smaller than doing a digital equivalent of an analog
PLL though.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email (e-mail address removed)
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
setup where the increment value got bumped up/down depending on the phase of the
accumulator vs the reference. Works quite well as long as the reference is
fairly stable. In our case we needed to track a mechanical system which had a
fairly high variance on the reference, so we wound up putting a lot of extra
crap on the design to improve the transient response without it going into
oscillation. Still lots smaller than doing a digital equivalent of an analog
PLL though.
Jason said:Hello guru's
I was wondering if anyone has ever attempted a phase lock loop in digital
before (specifically VHDL). I'm looking for some examples or pointers on
trying to build one for a low frequency range of 200 Hz to 200 kHz. I would
appreciate any comments or suggestions. Google didn't get me very far, so if
you know of any app notes, etc. please let me know.
Thanks,
Jason
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email (e-mail address removed)
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759