Re: Analysis and Design

Discussion in 'VHDL' started by ben cohen, Jun 26, 2003.

  1. ben cohen

    ben cohen Guest

    "Jörg Breitenstein" <> wrote in message news:<3ef972aa$0$1053$>...
    > Hi
    > Does anyone now if there is a good methologie to analyse and design digital
    > systems. There are plenty of books about VHDL, but that's the language. I'm
    > looking for somenthing like SA/SD or UML for software Design. But this vor
    > digital hardware.
    > Does Ben Cohen's Book cover topics like this?
    > Vhdl Coding Styles and Methodologies.
    > ???
    > Thanx
    > Joerg

    No my books do not cover structured ananlysis and structured design
    (SA/SD), nor UML. However, an interesting methodology that is gaining
    popularity is assertion-based design with PSL. Assertion-based
    verification (ABV) with Property Specification Language (PSL) is
    changing the traditional design process because that methodology helps
    to formally characterize the design intent and expected operations,
    guides the verification task, and eases the design of the testbench
    because it transfers more of the "verifier" task onto PSL, instead of
    a user defined model. My latest book addresses PSL by example.
    Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
    Author of following textbooks:
    * Using PSL/SUGAR with Verilog and VHDL
    Guide to Property Specification Language for ABV, 2003 isbn
    * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
    * Component Design by Example ", 2001 isbn 0-9705394-0-1
    * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
    * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
    ben cohen, Jun 26, 2003
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.

Share This Page