Re: Anyone familiar with TAR_DLY?

Discussion in 'VHDL' started by Andy Peters, Nov 18, 2005.

  1. Andy Peters

    Andy Peters Guest

    krby_xtrm wrote:
    > TAR_DLY is a signal from the backend of PCI Interface, but i dont know
    > the exact details.
    >
    > and is sited here:
    > http://www.eetimes.com/editorial/1995/fpgafeature9502.html


    "turn-around delay"?

    It's not a standard PCI signal. It's probably an implementation
    detail.

    -a
     
    Andy Peters, Nov 18, 2005
    #1
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  2. "Andy Peters" <> writes:

    > krby_xtrm wrote:
    >> TAR_DLY is a signal from the backend of PCI Interface, but i dont know
    >> the exact details.
    >>
    >> and is sited here:
    >> http://www.eetimes.com/editorial/1995/fpgafeature9502.html

    >
    > "turn-around delay"?


    Target-delay. It's apparently used when the Target of a PCI
    transaction wants to delay returning the data to the Master
    (initiator) of the cycle.

    > It's not a standard PCI signal. It's probably an implementation
    > detail.


    Definitely.


    Kai
    --
    Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>
     
    Kai Harrekilde-Petersen, Nov 18, 2005
    #2
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