Re: Avoiding latches

Discussion in 'VHDL' started by Keith R. Williams, Jul 14, 2003.

  1. In article <>, prv3299
    @yahoo.com says...
    > Hello! I got the following code which obviously creates latches. (It
    > is not clocked)
    >
    > CASE ad(10 DOWNTO 4) IS
    > WHEN b"011_0000" =>
    > CASE ad(3 DOWNTO 1) IS
    > WHEN "000" => dout <= msacom_reg;
    > WHEN OTHERS =>
    > END CASE;
    > WHEN b"011_0001" => dout <= ccm_txd;
    > WHEN b"011_0010" => IF (rx_page = '0') THEN dout <= ccm_rxd1;
    > ELSE dout <= ccm_rxd0;
    > END IF;
    > WHEN OTHERS =>
    > END CASE;
    >
    > Dout is also generated by other processes.


    If Dout is also generated by other processes, you *must* guarantee that
    they don't drive a '1' or '0' into each other. The magic smoke will
    be released.

    > I could clock the process
    > but then the latency would not be good. Can I add "dout <= (others =>
    > 'Z')" to the "WHEN OTHERS" part?


    Ok. That gives you a high impedance when none of the other cases is
    valid.

    > BTW, it works good with the latch but
    > since I always heard a latch is bad I'm not really sure what to do
    > besides adding a clock (which timing wise, would not be good).


    If you don't want the synthesizer to infer latches you must have all
    signals defined in all states. Since your Dout is defined in all states
    except "others", adding dout to the "when others" clauses (both of
    them) should get rid of your unwanted latches.

    Remember, latches get inferred when there is a state for which a
    variable/signal is undefined. It "remembers" the value it had in the
    last state, thus it is latched.

    --
    Keith
     
    Keith R. Williams, Jul 14, 2003
    #1
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