Re: change with sums and shifts

Discussion in 'VHDL' started by Martin Thompson, Oct 14, 2010.

  1. tommy <> writes:

    > hello guys!
    >
    > I 've a question how can i change this istructions in my structural
    > with simple sums and shifts operations?
    >
    > pOut <= CONV_STD_LOGIC_VECTOR((2* CONV_INTEGER(pIn) + 1), bitWidth/2 + 1);
    >
    > pOut <= CONV_STD_LOGIC_VECTOR((2* CONV_INTEGER(pIn)), bitWidth/2 + 1);
    >
    > thank you in advance
    >


    First, use the numeric_std libraries instead of conv_*:

    http://www.parallelpoints.com/node/3

    Second, why do you want to change to sums and shifts? Does the code
    not do what you want?

    Cheers,
    Martin

    --
    Martin Thompson, Oct 14, 2010
    #1
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  2. Martin Thompson

    Hyuma

    Joined:
    Oct 14, 2010
    Messages:
    3

    yes it does, it's only to semplify all.
    Hyuma, Oct 14, 2010
    #2
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  3. Martin Thompson

    Andy Guest

    On Oct 14, 5:33 am, Martin Thompson <> wrote:
    > tommy <> writes:
    > > hello guys!

    >
    > > I 've a question how can i change this istructions in my structural
    > > with simple sums and shifts operations?

    >
    > > pOut <= CONV_STD_LOGIC_VECTOR((2* CONV_INTEGER(pIn) + 1), bitWidth/2 + 1);

    >
    > > pOut <= CONV_STD_LOGIC_VECTOR((2* CONV_INTEGER(pIn)), bitWidth/2 + 1);

    >
    > > thank you in advance

    >
    > First, use the numeric_std libraries instead of conv_*:
    >
    > http://www.parallelpoints.com/node/3
    >
    > Second, why do you want to change to sums and shifts?  Does the code
    > not do what you want?
    >
    > Cheers,
    > Martin
    >
    > --



    It would be cleaner if you used numeric_std, but I have seen synopsys
    refuse to synthesize mult, div or mod of numeric_std.unsigned by
    integral powers of two (many years ago, so they may have fixed it).

    Unless this is a homework assignment, and you have been directed to
    code it with a shift and a sum, then any synthesis tool worth its salt
    will in fact implement your code as a shift and sum (actually shift
    and stuff). You don't have to do anything to get it.

    But here it is anyway:

    if input >= to_comp then
    output <= '1';
    nOut <= input - to_comp;
    pOut <= pIn(bitwidth - 2 downto 0) & '1';
    else
    output <= '0';
    nOut <= input;
    pOut <= pIn(bitwidth - 2 downto 0) & '0';
    end if;

    Unless directed to do otherwise (sometimes by a poor tool that won't
    work unless you spell it out for it), I would use the form that is
    easiest to understand the BEHAVIOR you want, not the implementation
    you want. Does the algorithm need to do a shift and stuff, or does it
    need to do a scale and add?

    Andy
    Andy, Oct 14, 2010
    #3
  4. Martin Thompson

    Andy Guest

    My bad, it should be pin(bitwidth / 2 - 1 downto 0). If the
    concatenation of the portion of pin and the 0 or 1 are to fit in pout,
    then you must reduce the size of pin by one, and on the left end, thus
    bitwidth / 2 - 1 is the MSB of the portion of Pin that is transferred
    to pout.

    Andy
    Andy, Oct 14, 2010
    #4
  5. Martin Thompson

    Andy Guest

    On Oct 14, 12:02 pm, tommy <> wrote:
    > Il 14/10/2010 18:48, Andy ha scritto:
    >
    > > My bad, it should be pin(bitwidth / 2 - 1 downto 0). If the
    > > concatenation of the portion of pin and the 0 or 1 are to fit in pout,
    > > then you must reduce the size of pin by one, and on the left end, thus
    > > bitwidth / 2 - 1 is the MSB of the portion of Pin that is transferred
    > > to pout.

    >
    > > Andy

    >
    > Ok, now works! And is correct i think, and no need to change the
    > istruction in test bench where i have input <= conv_std_logic_vector(i,16).
    > I'm not sure if I've understood the problem why need to do bitwidth/2
    > -1. Just before of this error I have pIn(8:0) & '1' in the if statement
    > and pIn(8:0) & 0 in else condition.
    > Now with your correction pIn take (7:0) i.e. 8 bit. you said that i need
    > to reduce the size by one, but why I need reduce? I can't use pOut as 9
    > bit? In port defintion I have pout defined like:
    >
    > pOut : out std_logic_vector( bitWidth/2 downto 0)
    >
    > Mine is only curiosity to understand well the problem.
    > Thanks again


    Adding a single bit (with a "+") does not increase the size of the
    result, but concatenating (with a "&") does.

    If pin and pout are the same size, you cannot fit pin and an extra bit
    into pout. So you either need to expand pout or reduce pin by one bit,
    to allow room for the extra LSB. I showed reducing pin by one bit
    (discarded the MSB).

    Andy
    Andy, Oct 15, 2010
    #5
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