Re: complement???

Discussion in 'VHDL' started by Pieter Hulshoff, Aug 17, 2003.

  1. > Please, can anybody tell me why do I get e as a complement of a when I
    > simulate this examle in Aldec's AHDL with waveform?


    The complement is caused because your process is only called once on a
    change of a, causing e to always lag one change behind a. I don't know
    exactly what this design is supposed to do, but if you wish to just connect
    a to e, why not settle for e <= a? If you insist on using connect, then at
    least place it in the sensitivity list or in the wait on list:

    barrel: PROCESS (a, e) IS
    BEGIN
    connect <= a;
    e <= connect;
    END PROCESS barrel;

    or

    barrel: PROCESS IS
    BEGIN
    connect <= a;
    e <= connect;
    WAIT ON a, connect;
    END PROCESS barrel;

    Regards,

    Pieter Hulshoff
     
    Pieter Hulshoff, Aug 17, 2003
    #1
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