Re: Connection of inouts

Discussion in 'VHDL' started by info_, Apr 15, 2005.

  1. info_

    info_ Guest

    René Bøje Nielsen wrote:
    > Hi all,
    >
    > I have a question concerning connection of bidirectional signals.
    >
    > Consider the code below. The attempt is to make a wrapper, which blasts a
    > component consisting of a std_logic_vector into separate std_logics. Both
    > the instantiated component's and the blasting entity's ports are defined as
    > inouts. The challenge now is to connect index 0 of the std_logic_vector with
    > the sl0 port and index 1 of the std_logic_vector with the sl1 port in a
    > bidrectional manner.


    I read this in a hurry ...
    but it looks like you're trying to model a kind of "wire".
    If that's the case, then Ben has done it before :)

    See http://members.aol.com/vhdlcohen/vhdl/Models.html

    Hope this helps,

    Bert Cuzeau
     
    info_, Apr 15, 2005
    #1
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