Re: Conversion of sequential time-sensitive algorithm to VHDL

Discussion in 'VHDL' started by Oliver Mattos, Feb 4, 2011.

  1. Yes - unfortunately stabilizability is a requirement...

    good plan otherwise though - certainly a minimal effort solution, and thats good :)
    Oliver Mattos, Feb 4, 2011
    #1
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  2. Oliver Mattos

    Dal Guest

    Is the sequence always the same or does can a host change the sequence
    of events?

    On Feb 5, 5:21 am, Oliver Mattos <> wrote:
    > Yes - unfortunately stabilizability is a requirement...
    >
    > good plan otherwise though - certainly a minimal effort solution, and thats good :)
    Dal, Feb 5, 2011
    #2
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