Re: Count bits in VHDL, with loop and unrolled loop producesdifferent results

Discussion in 'VHDL' started by Gabor Sz, Mar 5, 2011.

  1. Gabor Sz

    Gabor Sz Guest

    On Friday, March 4, 2011 3:08:59 PM UTC-5, JustJohn wrote:
    [snip]
    >
    > Yesterday, Gabor posted 35 6-input LUTs.
    > Gabor, what code did you use?


    I posted the Verilog, it's just a simple loop.
    The difference was targeting V6 in XST 12.1
    Looking through the synthesis report it became
    apparent that there are some new templates for
    "adder tree" that show up in the V6 implementation
    but not for V5. This seems to be the reason
    for the dramatic reduction going from V5 to V6
    while both have 6-input LUT's. Only XST for V6
    has the adder tree templates, so it got 65 LUT's
    down to 35. I haven't really thought about an
    optimal implementation for 6-input LUT's but given
    the fact that XST inferred a tree structure, it's
    probably pretty close to optimal already.

    -- Gabor
     
    Gabor Sz, Mar 5, 2011
    #1
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