Re: Delta delay in vhdl

[Harry Athanassiadis]

is the simulation cycle
Harry A

 

[anupam]

hi,
Every signal inside the process is assigned value after a delay callled
"delta delay".
Inside a process variabes are assigned values then and there while the
new values to the signals are updated only when the whole process is
scanned.
This means any updated value on the signal is not considered as new
value for the rest of the lines of code at a particular clk cycle.
eg:lets say a has '0' initially
process(clk,reset)
a<= '1';
b<=a;
end process;
At first clock though code is executed sequentially the new value(i.e,
1) of a is not assigned to b.
So all the values are assigned after delta delay so when the simulator
reaches b<=a statement the value of a is still 0 since detla delay is
not elapsed.

regards,
Anupam Jain

 

[srikanth.padava]

delta cycle??

That was a good explanation by Alan Fitch. But i still have a basic question regarding the delta cycle. It has really got on to my head now. I hope some one could help me out with this.

As alan described in his post that a
1. delta cycle = evaluation phase+update phase.
2. and i have read that a signal gets updated only after one delta cycle delay.
i.e if a process has a stmt a=1;(im using systemc) and deltacount =0, it should be updated in the next cycle.
3. but from alan, if stmt a=1 gets evaluated in the present deltacycle, and gets updated in the update phase(which is also in the same deltacycle, as it was told that delta cycle = evaluation phase+update phase.)

it would be great if some one explains me where ive got it wrong.

thanx a lot in advance,

srikanth.