Re: Delta delay in vhdl

Discussion in 'VHDL' started by Harry Athanassiadis, Dec 4, 2005.

  1. is the simulation cycle
    Harry A


    "priya" <> wrote in message
    news:...
    > Hi all?
    >
    > some one explain me what is delta delay in VHDL?
    >
    >
    >
    > regds,
    > priya
    >
     
    Harry Athanassiadis, Dec 4, 2005
    #1
    1. Advertising

  2. Harry Athanassiadis

    anupam Guest

    hi,
    Every signal inside the process is assigned value after a delay callled
    "delta delay".
    Inside a process variabes are assigned values then and there while the
    new values to the signals are updated only when the whole process is
    scanned.
    This means any updated value on the signal is not considered as new
    value for the rest of the lines of code at a particular clk cycle.
    eg:lets say a has '0' initially
    process(clk,reset)
    a<= '1';
    b<=a;
    end process;
    At first clock though code is executed sequentially the new value(i.e,
    1) of a is not assigned to b.
    So all the values are assigned after delta delay so when the simulator
    reaches b<=a statement the value of a is still 0 since detla delay is
    not elapsed.

    regards,
    Anupam Jain
     
    anupam, Dec 5, 2005
    #2
    1. Advertising

  3. Harry Athanassiadis

    srikanth.padava

    Joined:
    Feb 28, 2008
    Messages:
    3
    delta cycle??

    That was a good explanation by Alan Fitch. But i still have a basic question regarding the delta cycle. It has really got on to my head now. I hope some one could help me out with this.

    As alan described in his post that a
    1. delta cycle = evaluation phase+update phase.
    2. and i have read that a signal gets updated only after one delta cycle delay.
    i.e if a process has a stmt a=1;(im using systemc) and deltacount =0, it should be updated in the next cycle.
    3. but from alan, if stmt a=1 gets evaluated in the present deltacycle, and gets updated in the update phase(which is also in the same deltacycle, as it was told that delta cycle = evaluation phase+update phase.)

    it would be great if some one explains me where ive got it wrong.

    thanx a lot in advance,

    srikanth.
     
    srikanth.padava, Feb 28, 2008
    #3
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Ramakrishnan

    delta delay..

    Ramakrishnan, Sep 23, 2003, in forum: VHDL
    Replies:
    4
    Views:
    5,165
    Mike Treseler
    Sep 23, 2003
  2. srikanth.padava

    delta cycle?? (delta delay)

    srikanth.padava, Feb 28, 2008, in forum: VHDL
    Replies:
    0
    Views:
    1,130
    srikanth.padava
    Feb 28, 2008
  3. Trygve Odegaard

    Delta delay problem between multiple ports

    Trygve Odegaard, May 28, 2008, in forum: VHDL
    Replies:
    6
    Views:
    924
    Thomas Stanka
    Jun 2, 2008
  4. uj101
    Replies:
    9
    Views:
    668
    Mike Treseler
    Jul 30, 2008
  5. Roya
    Replies:
    4
    Views:
    1,502
Loading...

Share This Page