Re: demux model

Discussion in 'VHDL' started by rajan, Jul 3, 2003.

  1. rajan

    rajan Guest

    Sorry, I forgot to define 'one' here, which is:
    CONSTANT one : unsigned (15 DOWNTO 0) := (0 => '1', OTHERS => '0');

    "rajan" <> wrote in message
    news:CE%Ma.139291$...
    > Hello colleagues,
    >
    > I have a demux as below. Is there any other way to write it better in

    vhdl.
    >
    > -- 4to16 demux with shift_left operation --
    > wire_sig <= STD_LOGIC_VECTOR (shift_left(one, to_integer(unsigned
    > (wire_w))));
    >
    > regards,
    > rajan
    >
    >
     
    rajan, Jul 3, 2003
    #1
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