Re: demux model

Discussion in 'VHDL' started by Tim Hubberstey, Jul 4, 2003.

  1. rajan wrote:
    >
    > Hello colleagues,
    >
    > I have a demux as below. Is there any other way to write it better in vhdl.
    >
    > -- 4to16 demux with shift_left operation --
    > wire_sig <= STD_LOGIC_VECTOR (shift_left(one, to_integer(unsigned
    > (wire_w))));


    I seem to recall that I usually use something like:

    demux : process( wire_w )
    begin
    wire_sig <= (others => '0');
    wire_sig(to_integer(unsigned(wire_w)) <= '1';
    end process demux;
    --
    Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
    Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
    Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com
    Tim Hubberstey, Jul 4, 2003
    #1
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