Re: Design Issues

Discussion in 'VHDL' started by Kent, Jun 27, 2003.

  1. Kent

    Kent Guest

    Kai Harrekilde-Petersen <> wrote in message news:<>...
    > (stephen henry) writes:
    >
    > > 3. I have to generate a high speed pipeline, used to append and decode
    > > CRC's, (De)Scramble the datastream, and encode it into 8B10B.
    > > Additionally, i have to insert a number of primitive characters to
    > > control the flow of data across the link. I was told by one of my
    > > lecturers that the 8b10b section should be implemented serially, for
    > > speed, which got me wondering if i should also implement the CRC and
    > > Scrambler serially as well (which i had previously implemented
    > > parallel).

    >
    > Serially as in 1 bit at a time? - forget it. 8B/10B should be
    > implemented as a parallel thing, taking 8 bits + control per cycle,
    > and yielding the corresponding 10bit codegroup. Get the patent (IIRC
    > $3 from Delphion as a .pdf file) - it is very readable.
    >
    > As for the CRC, I wouldn't do that serially either. I'd do it 8bit at
    > a time, unless speed required me to go to bigger widths.
    >
    > Good luck,
    >
    >
    > Kai


    Actually if you look at a book called "Fibre Channel for SANS" a much
    more compact way to do it is 5B/6B and 3B/4B and cascade for the
    current running disparity.

    If you use a ROM lookup table and treat the input as an address and
    the output as the decoded/encoded result, you can implement 8B/10B
    with cycle times as fast as the access time of your ROM.

    Kent
    Kent, Jun 27, 2003
    #1
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