Re: Digital PLL

Discussion in 'VHDL' started by rupesh.raghatate@gmail.com, Jun 21, 2013.

  1. Guest

    On Thursday, 11 April 2002 13:53:01 UTC+5:30, Roberto Capobianco wrote:
    > Hi all, could you suggest me some methods to realize a digital PLL in VHDL different from that used in USB (www.usb.org/developers/data/siewp.pdf). In particular is possible to avoid ripple clock ?--Roberto Capobianco Consorzio RFX - CNR di PadovaC.so Stati Uniti, 435127 - Camin (PD) email: : www.igi.pd.cnr.it tel.: +39-049-8295048fax: +39-049-8700718


    dear sir ,
    i am trying to design dpll using vhdl could you please suggest me some book or refrence papers on any thing


    thanks
    regards
    Rupesh Raghatate
    asst prof AVBIT,pawnar ,INDIA
     
    , Jun 21, 2013
    #1
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