Re: discrepency between behavioral simulation and post routesimulation

Discussion in 'VHDL' started by JimLewis, Nov 25, 2009.

  1. JimLewis

    JimLewis Guest

    Hi Karl,
    Advice: Take a training class, they will get you doing testbenches
    right.

    First setup clock.
    Next drive reset for several clocks and deassert it with
    respect to clock plus a propagation delay.
    Next Drive stimulus with a propagation delay with respect to clock.

    For your gate simulation, make sure to back annotate at least
    nominal timing - without it, you may be failing due to delta
    cycle races that are not in the real circuit.

    Make sure your design double samples reset before distributing
    it to your circuit.



    architecture test of testbench is
    constant tperiod_Clk : time := 20 ns ;
    constant tpd : time := 2 ns ; -- representationve prop delay

    signal clk : std_logic := '0' ;
    . . .

    begin

    Clk <= not Clk after tperiod_Clk ;

    -- leave reset asserted for a while
    DriveReset : process
    begin
    Reset <= 'X' ; -- unknown at start
    wait until Clk = '1' ; -- rising edge clk
    Reset <= '1' after 2.5 * tperiod_Clk, '0' after 10 * tperiod_Clk +
    tpd ;
    wait ;
    end process ;


    DriveStimulus : process
    begin
    wait until Reset = '0' ; -- out of reset
    wait until Clk = '1' ;
    wait until Clk = '1' ;

    data <= "1010" after tpd ;
    wait until Clk = '1' ; -- wait 2 clocks are part of symbol
    processing
    wait until Clk = '1' ;

    data <= "0010" after tpd ;
    wait until Clk = '1' ;
    wait until Clk = '1' ;

    data <= "1110" after tpd ;
    wait until Clk = '1' ;
    wait until Clk = '1' ;

    data <= "1110" after tpd ;
    wait until Clk = '1' ;
    wait until Clk = '1' ;

    wait for 10 * tperiod_Clk ;
    -- report "Just Kidding" severity failure ; -- old way to stop
    the sim
    std.env.stop(0) ; -- new way to stop a sim, supported by
    ModelSim + Aldec
    end process ;


    You will learn this and more about testbenches in our
    Comprehensive VHDL Introduction classes.

    Best,
    Jim Lewis
    VHDL Training Guru
    http://www.synthworks.com
    JimLewis, Nov 25, 2009
    #1
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  2. JimLewis

    KJ Guest

    On Nov 25, 6:22 pm, JimLewis <> wrote:

    Given the name of the constant...
    >   constant tperiod_Clk : time := 20 ns ;


    The assignment below is not quite right...
    >   Clk <= not Clk after tperiod_Clk ;
    >


    It should be...
    Clk <= not Clk after (tperiod_Clk / 2);

    I generally write it as...
    Clk <= not(Simulation_Complete) and not Clk after (tperiod_Clk / 2);

    Where 'Simulation_Complete' is a signal set by the testbench to
    indicate when the simulation is completing. That way instead of
    ending like this which throws an assertion failure...

    >      wait for 10 * tperiod_Clk ;
    >      -- report "Just Kidding" severity failure ;  -- old way to stop
    > the sim


    One can end in a graceful manner like this...
    Simulation_Complete <= '1';
    report "Simulation completed";
    wait;

    I don't use the hammer to stop the sim...
    >      std.env.stop(0) ;  -- new way to stop a sim, supported by
    > ModelSim + Aldec


    But do appreciate that there is a hammer that I might want to use in
    the future.

    Kevin Jennings
    KJ, Nov 26, 2009
    #2
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  3. JimLewis

    karl bezzoto Guest

    Many thanks for your answers. i'll try them later and let them know
    how it goes.
    karl bezzoto, Nov 26, 2009
    #3
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