Re: Dynamic Configuration Possibility in Modelsim ?

Discussion in 'VHDL' started by Allan Herriman, Aug 28, 2003.

  1. Francisco Camarero wrote:
    > Hello!
    >
    > The design I am currently working with (E0) makes
    > two instances (U1 and U2) of a component defined by
    > the entity E1 that has several architecture
    > versions, in my case up to 4.
    >
    > I hope this code extract helps to explain myself:
    >
    > entity E1 is
    > ..
    > end E1;
    >
    > architecture A1 of E1 is
    > ..
    > end architecture A1;
    >
    > architecture A2 of E1 is
    > ..
    > end architecture A2;
    >
    > architecture A3 of E1 is
    > ..
    > end architecture A2;
    >
    > architecture A4 of E1 is
    > ..
    > end architecture A2;
    >
    >
    > entity E0 is
    > ..
    > end E0;
    >
    > architecture A0 of E0 is
    > ..
    > component E1
    > ..
    > begin
    > ..
    > U1: E1
    > ..
    > U2: E1
    > ..
    > end architecture A0;
    >
    >
    > I am using Modelsim, and I would like to be able
    > to choose which configuration to use for the E1s
    > when I call vsim.
    >
    > Currently I would have to use 16 different VHDL configurations
    > for this purpose:
    >
    >
    > configuration C11 of E0 is
    > for A0
    > for U1 : E1
    > use entity work.E1(A1);
    > end for;
    > for U2 : E1
    > use entity work.E1(A1);
    > end for;
    > end for;
    > end configuration C0;
    >
    > configuration C12 of E0 is
    > for A0
    > for U1 : E1
    > use entity work.E1(A1);
    > end for;
    > for U2 : E1
    > use entity work.E1(A2);
    > end for;
    > end for;
    > end configuration C0;
    >
    > ..
    >
    > configuration C44 of E0 is
    > for A0
    > for U1 : E1
    > use entity work.E1(A4);
    > end for;
    > for U2 : E1
    > use entity work.E1(A4);
    > end for;
    > end for;
    > end configuration C0;
    >
    >
    >
    > Is there no more efficient way to do this ?
    >
    > Is there a posibility to give this configuration through
    > the vsim command line ? something like:
    >
    > vsim work.E0 U1=E1(A2) U2=E1(A2) ?



    You can specify a configuration on the vsim command line, in place of
    the top level entity (E0 in this case). This would still require 16
    configurations.

    You can also specify a generic on the command line with the
    -g<label>=<value> or -G<label>=<value> switches, and use an if-generate
    statement in your code to select the configuration.
    This requires 8 configurations (with two generics).

    Or, you could avoid configurations altogether, and use two sets of four
    if-generates that select the architecture directly (with two generics).


    Regards,
    Allan.
    Allan Herriman, Aug 28, 2003
    #1
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  2. Jonathan Bromley wrote:

    > "Francisco Camarero" <> wrote in
    > message news:...
    >
    >>I am sincerely thinking about having Perl or Tcl automatically
    >>generate the configuration file, compile it, and call vsim with
    >>the result.


    [big snip]

    Is there any *fundamental* reason why the name of a VHDL component (or
    entity or configuration) being instantiated has to be fixed?

    As long as it is globally static (i.e. known at elaboration time) it
    ought to be possible to use an expression to provide the component name.

    I have written modules (sorry, entity/architecture pairs) in the past
    that have just been a big series of if-generate statements, each around
    an instantiation that only differs in the name of the entity being
    instantiated. Being able to use a function to determine the entity name
    would reduce this code to a single instantiation.

    This, of course, would be a major change to the language and tools, and
    I'm not seriously proposing it as a change.

    Regards,
    Allan.
    Allan Herriman, Aug 29, 2003
    #2
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  3. Very nice!

    A little overkill for my needs, but I can start from here.

    Thanks!

    Fran.


    Jonathan Bromley wrote:
    > So I've
    > built a little macrogenerator in Tcl (which means, of course,
    > that you can run it from within ModelSim). It uses <n> as the
    > name of a macro, where n is any string of digits.
    > Each macro is given a list of possible values using
    > a metacomment line such as "--<1> A1 A2 A3 A4".
    > The macrogenerator collects together all these macro
    > definitions, and then does a substitution on the source
    > text, once for each possible combination of all the
    > macros' values. It works for any number of macros(!)
    > but here's the code that solves Francisco's problem:
    >
    > ~~~~~~~~~~~~~~~~ macro source file ~~~~~~~~~~~~~~~~~
    > ~~~~~~~ to be processed by the Tcl script ~~~~~~~~~~
    >
    > -- Automatically generated VHDL configuration
    > -- using architecture <1> for instance U1
    > -- and architecture <2> for instance U2
    > --
    > -- Here's the list of architectures to use
    > -- for the various substitutions:
    > --
    > --<1> A1 A2 A3 A4
    > --<2> A1 A2 A3 A4
    > --
    > --<begin>
    > configuration Cfg_<1>_<2> of E0 is
    > for A0
    > for U1 : E1
    > use entity work.E1(<1>);
    > end for;
    > for U2 : E1
    > use entity work.E1(<2>);
    > end for;
    > end for;
    > end configuration Cfg_<1>_<2>;
    > --<end>
    >
    > ~~~~~~~~~~~~~~ end of macro source file ~~~~~~~~~~~~
    >
    > And here's the Tcl script, or strictly speaking, the
    > bunch of Tcl procedures. Source this script into a
    > Tcl interpreter, then invoke the top-level proc
    >
    > build_configs sourcefile.vhd resultfile.vhd
    >
    > (with obvious changes to filenames as needed).
    >
    > It's left as a trivial exercise for the reader
    > to turn it into something robust and useful :)
    >
    > Does anyone know if the same thing is possible
    > using m4 or some existing macro processor?
    >
    > ~~~~~~~~~~~~~~~~Tcl script~~~~~~~~~~~~~~~~
    > # ConfigTemplate.tcl Jonathan Bromley, 28 Aug 2003
    > #
    > # This is a specialised macro preprocessor with the
    > # special property that each macro in the source code
    > # is given a LIST of possible replacement values.
    > # The macro substitution is then performed once for
    > # every possible combination of all the replacement
    > # values. So, for example, if your source text contains
    > # two macros, one with three possible values and the other
    > # with four possible values, you will get a result with
    > # twelve different copies of the original.
    > #
    > # The macro syntax is intended to be appropriate for
    > # VHDL code. You define a macro, and its list of possible
    > # replacement values, in a VHDL comment thus:
    > # --<n> rep1 rep2 rep3 ...
    > # where n is any string of digits, and rep1... are the
    > # possible replacements which MUST NOT CONTAIN the
    > # special characters backslash, square brackets,
    > # dollar sign or curly brackets. Note there is NO
    > # whitespace between the comment marker and the angle
    > # bracket.
    > # Typically you will not want these macro definitions
    > # to appear in the resulting text, so special metacomments
    > # --<begin> and --<end> mark the beginning and end of
    > # the text that will be macro-replaced; anything outside
    > # these markers will not be replaced. Within these
    > # markers, however, any occurrence of a macro name <n>
    > # will be replaced with the corresponding macro value.
    >
    > # _________________________________________________ linecount ___
    > #
    > # Just a utility procedure for debugging.
    > #
    > proc linecount {s} {
    > return [llength [split $s "\n"]]
    > }
    >
    > # __________________________________________ make_substitution ___
    > #
    > # proc make_substitution performs exactly one round
    > # of macro substitution. $template is the substitutable
    > # template text taken from between --<begin> and --<end>.
    > # "replacements" is a list with two elements for each macro:
    > # the macro name (like <1>) and the replacement value.
    > # The result value is the entire substituted text.
    > #
    > proc make_substitution {template replacements} {
    > foreach {macro value} $replacements {
    > regsub -all $macro $template $value template
    > }
    > return $template
    > }
    >
    > # ____________________________________________ make_substLists ___
    > #
    > # This procedure iterates over all macros to create the
    > # cross-product of all macro replacements. It does this by
    > # iterating over all values of the first macro in the list,
    > # recursively calling itself for all remaining macros in
    > # the list.
    > #
    > proc make_substLists {
    > remainingMacros baseSubst resultVar replacementArray
    > } {
    >
    > # Get access to the array of substitution values
    > upvar $replacementArray rA
    > # Get access to the result list
    > upvar $resultVar rV
    >
    > if {[llength $remainingMacros]}
    >
    > # More macros to scan recursively. Get the macro to scan over:
    > set macro [lindex $remainingMacros 0]
    > # And scan over all its possible values:
    > foreach value $rA($macro) {
    > make_substLists \
    > [lrange $remainingMacros 1 end] \
    > [concat $baseSubst $macro $value] \
    > rV rA
    > }
    > } else
    >
    > # No more to scan
    > lappend rV $baseSubst
    > puts -nonewline "INFO: Adding substitution"
    > foreach {macro value} $baseSubst {
    > puts -nonewline " $macro=$value"
    > }
    > puts {}
    > }
    > }
    >
    > # ________________________________________ build_configs ___
    > #
    > # This is the top-level procedure.
    > # Give it two filenames: the source file (containing
    > # all the macro definitions etc) and the name of a
    > # result file, which will be created (overwriting
    > # any existing file of the same name).
    > #
    > proc build_configs {template_file result_file} {
    >
    > # Slurp the template file
    > set f_template [open $template_file r]
    > set template {}
    > while {![eof $f_template]} {
    > append template [read $f_template]
    > }
    > close $f_template
    > puts "INFO: Read [linecount $template] lines from template file"
    >
    > # Find the lists of substitutions by looking for
    > # all --<n> macros.
    > set substitutions \
    > [regexp -inline -all -linestop -- {--<\d+>.*} $template]
    >
    > # Pick the meaningful VHDL out of that template
    > # by extracting all text between the --<begin>
    > # and --<end> macros
    > regexp -- {--<begin>(.*)--<end>} $template -> template
    > puts "INFO: Found [linecount $template] lines of useful code"
    >
    > # Process each substitution line to extract the <n> macro and
    > # the list of substitution values. Build a Tcl array of
    > # these substitution lists, indexed by the macro.
    > foreach s $substitutions {
    > regexp -- {--(<\d+>)(.*)$} $s -> macro substList
    > set replacements($macro) $substList
    > }
    > set macros [lsort -dictionary [array names replacements]]
    > puts "INFO: Found macros: $macros"
    >
    > # Make a list of substitution-lists
    > set substList {}
    > make_substLists $macros {} substList replacements
    >
    > # Open the result file
    > set f_result [open $result_file w]
    >
    > # For each substitution-list, add the substituted text to
    > # the output file
    > foreach reps $substList {
    > puts $f_result [make_substitution $template $reps]
    > }
    >
    > # We're done
    > close $f_result
    > puts "INFO: Result created in file $result_file"
    > }
    > ~~~~~~~~~~~~ end of Tcl script ~~~~~~~~~~~~~~~~~~~~~~~~
    > --
    > Jonathan Bromley, Consultant
    >
    > DOULOS - Developing Design Know-how
    > VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services
    >
    > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
    > Tel: +44 (0)1425 471223 mail:
    > Fax: +44 (0)1425 471573 Web: http://www.doulos.com
    >
    > The contents of this message may contain personal views which
    > are not the views of Doulos Ltd., unless specifically stated.
    Francisco Camarero, Aug 29, 2003
    #3
  4. "Francisco Camarero" <> wrote in
    message news:...

    [re my Tcl macrogenerator script...]

    > Very nice!
    > A little overkill for my needs, but I can start from here.


    Nicer with this bugfix:

    # Pick the meaningful VHDL out of that template
    # by extracting all text between the --<begin>
    # and --<end> macros
    # FIX: Allow arbitrary comment text on the --<begin> line
    regexp -lineanchor -- {--<begin>.*?$(.*)--<end>} $template -> template

    --

    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Aug 29, 2003
    #4
  5. Jonathan Bromley wrote:
    > "Allan Herriman" <> wrote in
    > message news:...
    >
    >
    >>Is there any *fundamental* reason why the name of a VHDL component (or
    >>entity or configuration) being instantiated has to be fixed?

    >
    >
    > %SYS-F-BRAINOVFL, Fatal error: Question too hard.
    >
    >
    >>As long as it is globally static (i.e. known at elaboration time) it
    >>ought to be possible to use an expression to provide the component name.

    >
    >
    > I've had a run-in with some VHDL experts on this before. In
    > general, determining whether an expression is a constant is
    > too hard for compilers to solve - and VHDL has chosen not to
    > take the weasel path of imposing a bunch of arbitrary conditions
    > to make the problem easy. Whether this is a good thing is
    > another matter.
    >
    >
    >>I have written modules (sorry, entity/architecture pairs) in the past
    >>that have just been a big series of if-generate statements, each around
    >>an instantiation that only differs in the name of the entity being
    >>instantiated. Being able to use a function to determine the entity name
    >>would reduce this code to a single instantiation.

    >
    >
    > Forgive my dim question, but isn't this what the indirection of
    > component+configuration is intended to solve?


    Probably.

    I've avoided using them because of tool support has been rather poor (in
    the past). I trust it is better now.
    I've moved to Verilog so I won't get the chance to try them :(

    Regards,
    Allan.
    Allan Herriman, Aug 29, 2003
    #5
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