Re: event in state machine

Discussion in 'VHDL' started by A. Smalls, Jun 25, 2003.

  1. A. Smalls

    A. Smalls Guest

    Hi Troels,
    Is there any reason that you can not use a Flop with and an enable
    in the idle state to "latch" the value of the signal and then just
    compare that to the incoming signal in the wait4lr state and
    transition if the values are not the same?



    (Troels Smit) wrote in message news:<>...
    > Hi all,
    >
    > I have to change state on the event change of a signal - so I wrote
    > the following posted below.
    >
    > when wait4lr =>
    > if lr'event then
    > next_state <= wait20sclk_and4_cordic;
    > end if;
    >
    > This give a bad synchronous description of my "next_state" signal. How
    > does one work around the problem that you need to switch state on the
    > changing of a signal ?
    >
    >
    > /Troels
    >
    >
    >
    >
    >
    >
    > The Code (for reference):
    >
    > state_logic : process (lr, current_state, counter20f, cordic_rfd,
    > cordic_rdy)
    > begin -- process state_logic
    > case current_state is
    > when idle =>
    > next_state <= wait4lr;
    > when wait4lr =>
    > if lr'event then --ERRROR
    > next_state <= wait20sclk_and4_cordic;
    > end if;
    > when wait20sclk_and4_cordic =>
    > if (counter20f = '1' and cordic_rfd = '1') then
    > next_state <= handshake_cordic;
    > end if;
    > when handshake_cordic =>
    > if cordic_rdy = '1' then
    > next_state <= read_output;
    > end if;
    > when read_output =>
    > next_state <= wait4lr;
    > end case;
    > end process state_logic;
    >
    >
    >
    > state_change : process (clk, reset)
    > begin -- process state_change
    > if reset = '1' then -- asynchronous reset (active
    > high)
    > current_state <= idle;
    > elsif clk'event and clk = '1' then -- rising clock
    > edge
    > current_state <= next_state;
    > end if;
    > end process state_change;
     
    A. Smalls, Jun 25, 2003
    #1
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  2. A. Smalls

    Troels Smit Guest

    > Hi Troels,
    > Is there any reason that you can not use a Flop with and an enable
    > in the idle state to "latch" the value of the signal and then just
    > compare that to the incoming signal in the wait4lr state and
    > transition if the values are not the same?


    This doesn't comply 100% with the timing diagram, but indeed it works
    and I use something like this solution now - until taught better :)

    (Can't wait to see what code the other thread will result in!!)

    /Troels
     
    Troels Smit, Jun 26, 2003
    #2
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