Re: Examples of issues with std_logic_arith

Discussion in 'VHDL' started by Tricky, Mar 27, 2009.

  1. Tricky

    Tricky Guest

    Heres an interesting point.

    consider this:

    architecture sim of play_tb is
    constant ZERO_8 : std_logic_vector := x"00";
    constant ZERO_9 : std_logic_vector := b"0_0000_0000";
    begin

    process
    begin
    echo(boolean'image(ZERO_8 = ZERO_9) & LF);
    wait;
    end process;
    end architecture sim;

    if std_logic_unsigned is not included, this returns false (unmatched
    array lengths)
    if it is included, it returns true.

    Using numeric std (and not the synopsys packages) would allow this to
    always be false (as it possibly should). Basically the arith/unsigned/
    signed packages give meaning to std_logic_vectors, when they really
    shouldnt.
    Tricky, Mar 27, 2009
    #1
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