Re: fir decimation filter in VHDL

Discussion in 'VHDL' started by mindenpilot, Nov 19, 2005.

  1. mindenpilot

    mindenpilot Guest

    1. specify your filter performance
    2. design your filter in MatLab or QED, etc
    3. THEN implement in vhdl.

    Step 3 is the easy part. Just multiply and accumulate...
    IF you get to step three and still have questions, let me know...

    "saras" <> wrote in message
    news:...
    > hi..
    > thanks!
    > Actually I want to design FIR decimation filter.This is a project
    > which is done for study purpose.I am a starter in vhdl.Please give me
    > suggestions.
    >
    >
    >
    >
    > mindenpilot wrote:
    >
    >> "saras" <> wrote in message
    >> news:...
    >> > Thanks! for the reply .We have already used core generators in our
    >> > design but my PM wants me to do this on my own. Any suggestions like
    >> > which structures is bettter for implementation in VHDL and about
    >> > windowing techniques(hamming or rectangular ) etc..
    >> >
    >> > Also , I want to know which tecnique is used in xilinx filter core
    >> >

    >>
    >> What is your application?
    >> What are you doing, exactly?
    >> Your questions seem a bit vague.
    >> Do you want to implement a decimation filter or a windowing function?
    >> Both can be done as FIR...

    >
     
    mindenpilot, Nov 19, 2005
    #1
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  2. mindenpilot

    saras Guest

    thanks!!!!!!! a lot for your suggestions .I will surely let u know
    if I have any diffficulties.
    thx! once again.
    mindenpilot wrote:
    > 1. specify your filter performance
    > 2. design your filter in MatLab or QED, etc
    > 3. THEN implement in vhdl.
    >
    > Step 3 is the easy part. Just multiply and accumulate...
    > IF you get to step three and still have questions, let me know...
    >
    > "saras" <> wrote in message
    > news:...
    > > hi..
    > > thanks!
    > > Actually I want to design FIR decimation filter.This is a project
    > > which is done for study purpose.I am a starter in vhdl.Please give me
    > > suggestions.
    > >
    > >
    > >
    > >
    > > mindenpilot wrote:
    > >
    > >> "saras" <> wrote in message
    > >> news:...
    > >> > Thanks! for the reply .We have already used core generators in our
    > >> > design but my PM wants me to do this on my own. Any suggestions like
    > >> > which structures is bettter for implementation in VHDL and about
    > >> > windowing techniques(hamming or rectangular ) etc..
    > >> >
    > >> > Also , I want to know which tecnique is used in xilinx filter core
    > >> >
    > >>
    > >> What is your application?
    > >> What are you doing, exactly?
    > >> Your questions seem a bit vague.
    > >> Do you want to implement a decimation filter or a windowing function?
    > >> Both can be done as FIR...

    > >
     
    saras, Nov 21, 2005
    #2
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