Re: fir decimation filter in VHDL

Discussion in 'VHDL' started by Maarten, Nov 19, 2005.

  1. Maarten

    Maarten Guest

    > I want to design a FIR decimation filter using VHDL using 1
    > multiplier and not using any of the core generators provided by xilinx.
    > Please give me suggestions.



    In general calculations preferably are performed at lowest clock speed =>
    for downsampler therefore at target data rate.
    However: all input samples shall be used to calculate new samples.
    Therefore: when downsampling by factor two, make two parallel filter
    branches of which one utilises the odd input samples, the other branche the
    even input samples.

    example rtl-ish behaviour (sythesizable) architecture code for two times
    downsampling:


    --------------------------------------------------------------------------------

    -- Design Information

    --------------------------------------------------------------------------------

    --

    -- Design Unit : decimate_by_two

    --

    -- File Name : decimate_by_two_behaviour.a.vhdl

    --

    -- Function : to downsample by factor 2

    --

    --------------------------------------------------------------------------------





    ARCHITECTURE behaviour OF decimate_by_two IS

    SUBTYPE integer8s IS integer RANGE 127 DOWNTO -128;

    SUBTYPE integer10u IS integer RANGE 1023 DOWNTO 0;

    SUBTYPE integer18s IS integer RANGE 131071 DOWNTO -131072;

    SUBTYPE integer20s IS integer RANGE 524287 DOWNTO -524288;

    SUBTYPE integer21s IS integer RANGE 1048575 DOWNTO -1048576;

    TYPE delay_line_in IS ARRAY(0 TO 5) OF integer10u;

    TYPE delay_line_gain_result IS ARRAY(0 TO 5) OF integer18s;

    TYPE delay_line IS ARRAY(0 TO 5) OF integer8s;

    TYPE coefdelay_line IS ARRAY(0 TO 1) OF delay_line;

    CONSTANT coeff : coefdelay_line := ((13, -23, 48, 101, -9, -2),

    (-2, -9, 101, 48, -23, 13));

    SIGNAL data_in_div_two : std_logic ;

    SIGNAL even_datain_array : delay_line_in := (OTHERS => 0);

    SIGNAL odd_datain_array : delay_line_in := (OTHERS => 0);

    SIGNAL even_datain_d : integer10u ;

    SIGNAL even_gain_result : delay_line_gain_result := (OTHERS => 0);

    SIGNAL odd_gain_result : delay_line_gain_result := (OTHERS => 0);

    SIGNAL filter_sum : integer21s ;



    BEGIN

    generate_data_in_div_two_proc:pROCESS(clk27)

    BEGIN

    if (clk27'event AND clk27 = '1') then

    if reset ='1'

    then data_in_div_two <= '0' ;

    else if data_valid_in = '1'

    then data_in_div_two <= NOT data_in_div_two ;

    else data_in_div_two <= data_in_div_two ;

    end if;

    end if;

    end if;

    END PROCESS generate_data_in_div_two_proc;

    register_inputs_proc:pROCESS(clk27)

    BEGIN

    if (clk27'event AND clk27 = '1') then

    if reset ='1' then

    for i in 0 to 5 loop

    odd_datain_array(i) <= 0 ;

    even_datain_array(i) <= 0 ;

    end loop;

    else if data_valid_in = '1'

    then if data_in_div_two = '1'

    then for i in 5 downto 1 loop

    odd_datain_array(i) <= odd_datain_array(i-1) ;

    even_datain_array(i) <= even_datain_array(i-1) ;

    end loop;

    odd_datain_array(0) <= to_integer(unsigned(data_in)) ;

    even_datain_array(0) <= even_datain_d ;

    else even_datain_d <= to_integer(unsigned(data_in)) ;

    end if;

    else NULL ;

    end if;

    end if;

    end if;

    END PROCESS register_inputs_proc;





    low_pass_filter_proc:pROCESS(clk27)

    variable data_out_t :std_logic_vector(10 DOWNTO 0);

    BEGIN

    if (clk27'event AND clk27 = '1') then

    if reset='1'

    then data_out <= (OTHERS=>'0');

    filter_sum <= 0;

    data_valid_out <= '1';

    for i in 0 to 5 loop

    even_gain_result(i) <= 0;

    odd_gain_result(i) <= 0;

    end loop;

    else if data_in_div_two ='1'

    then for i in 0 to 5 loop

    even_gain_result(i) <= coeff(0)(i)*even_datain_array(i);

    odd_gain_result(i) <= coeff(1)(i)*odd_datain_array(i);

    end loop;

    filter_sum <= even_gain_result( 0) +

    even_gain_result( 1) +

    even_gain_result( 2) +

    even_gain_result( 3) +

    even_gain_result( 4) +

    even_gain_result( 5) +

    odd_gain_result( 0) +

    odd_gain_result( 1) +

    odd_gain_result( 2) +

    odd_gain_result( 3) +

    odd_gain_result( 4) +

    odd_gain_result( 5) ;

    if (filter_sum < 0)

    then data_out <= (OTHERS=>'0');

    else data_out_t :=
    div_rnd(std_logic_vector(to_unsigned(filter_sum,21)),8,11);

    data_out <= data_out_t(9 DOWNTO 0);

    end if;

    data_valid_out <= '0';

    else data_valid_out <= (NOT data_in_div_two ) AND data_valid_in;

    end if;

    end if;

    end if;

    END PROCESS low_pass_filter_proc;

    END behaviour;
     
    Maarten, Nov 19, 2005
    #1
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  2. Maarten

    saras Guest

    thanks!!!!!!! a lot for your help . thx! once again.
     
    saras, Nov 21, 2005
    #2
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  3. Maarten

    ABS Guest

    hii...

    well i have designed an FIR filter and tested the code, well m workin
    on synthesis on the same and along with it learning the synthesis
    tool... well u seem to be an indian saras... m from bangalore.. wer u
    from??
     
    ABS, Nov 21, 2005
    #3
  4. Maarten

    saras Guest

    hi....

    m an indian from b'lore.Thx! for ur reply.U said that,u have worked on
    fir, I want to know if it is decimation filter or not.Plz , give me
    suggestions.Also, which synthesis tool u r working on??

    ABS wrote:
    > hii...
    >
    > well i have designed an FIR filter and tested the code, well m workin
    > on synthesis on the same and along with it learning the synthesis
    > tool... well u seem to be an indian saras... m from bangalore.. wer u
    > from??
     
    saras, Nov 21, 2005
    #4
  5. Maarten

    ABS Guest

    hii...

    welll cant disclose soo much as its an IP and m yet an intern in my
    company. what abt u, intern or confirmed... not asking or teling which
    company each r working in...
    well my design is not a decimation filter.
    design a simple FIR FILTER choose the no. of taps like 8 or 10 since
    its not a proj its just for u to learn the tool, so its gets easier. u
    have to scal multiply with the coeff add the result and scale the
    output. take help from people around u (seniors)...
    u done ur mtech or just BE and from wer??? if u dont mind saying..

    alrite..
    TC
    all the best
     
    ABS, Nov 22, 2005
    #5
  6. Maarten

    ABS Guest

    m woking on xilinx xst tool, 6.1.. m just getting started with the
    synthesis and posted a thread for asking info on the same...
     
    ABS, Nov 22, 2005
    #6
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