Re: Generic Parameters in top-level file

Discussion in 'VHDL' started by ALuPin, Jun 25, 2004.

  1. ALuPin

    ALuPin Guest

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;

    LIBRARY work;

    ENTITY zbt_ctrl_top IS
    port
    (
    CLK : IN STD_LOGIC;
    RESET : IN STD_LOGIC;
    RD_WR_N : IN STD_LOGIC;
    ADDR_ADV_LD_N : IN STD_LOGIC;
    ADDR : IN STD_LOGIC_VECTOR(17 downto 0);
    DATA_IN : IN STD_LOGIC_VECTOR(17 downto 0);
    DM : IN STD_LOGIC_VECTOR(3 downto 0);
    DQ : INOUT STD_LOGIC_VECTOR(17 downto 0);
    RW_N : OUT STD_LOGIC;
    ADV_LD_N : OUT STD_LOGIC;
    BW_N : OUT STD_LOGIC_VECTOR(3 downto 0);
    DATA_OUT : OUT STD_LOGIC_VECTOR(17 downto 0);
    SA : OUT STD_LOGIC_VECTOR(17 downto 0)
    );
    END zbt_ctrl_top;

    ARCHITECTURE bdf_type OF zbt_ctrl_top IS

    component addr_ctrl_out
    PORT(Clk : IN STD_LOGIC;
    Reset : IN STD_LOGIC;
    Lb_rw_n : IN STD_LOGIC;
    Lb_adv_ld_n : IN STD_LOGIC;
    Lb_addr : IN STD_LOGIC_VECTOR(17 downto 0);
    Lb_bw : IN STD_LOGIC_VECTOR(3 downto 0);
    Ram_rw_n : OUT STD_LOGIC;
    Ram_adv_ld_n : OUT STD_LOGIC;
    Ram_addr : OUT STD_LOGIC_VECTOR(17 downto 0);
    Ram_bw_n : OUT STD_LOGIC_VECTOR(3 downto 0)
    );
    end component;

    component data_inout
    PORT(Clk : IN STD_LOGIC;
    Reset : IN STD_LOGIC;
    Ctrl_in_rw_n : IN STD_LOGIC_VECTOR(17 downto 0);
    Data_in : IN STD_LOGIC_VECTOR(17 downto 0);
    Dq : INOUT STD_LOGIC_VECTOR(17 downto 0);
    Read_data : OUT STD_LOGIC_VECTOR(17 downto 0)
    );
    end component;

    component pipe_delay
    PORT(Clk : IN STD_LOGIC;
    Reset : IN STD_LOGIC;
    Lb_rw_n : IN STD_LOGIC;
    Lb_data_in : IN STD_LOGIC_VECTOR(17 downto 0);
    Ram_data_out : IN STD_LOGIC_VECTOR(17 downto 0);
    Delay_data_in : OUT STD_LOGIC_VECTOR(17 downto 0);
    Delay_rw_n : OUT STD_LOGIC_VECTOR(17 downto 0);
    Lb_data_out : OUT STD_LOGIC_VECTOR(17 downto 0)
    );
    end component;

    component pipe_stage
    PORT(Clk : IN STD_LOGIC;
    Reset : IN STD_LOGIC;
    Rd_wr_n : IN STD_LOGIC;
    Addr_adv_ld_n : IN STD_LOGIC;
    Addr : IN STD_LOGIC_VECTOR(17 downto 0);
    Data_in : IN STD_LOGIC_VECTOR(17 downto 0);
    Data_out : IN STD_LOGIC_VECTOR(17 downto 0);
    Dm : IN STD_LOGIC_VECTOR(3 downto 0);
    Rd_wr_n_reg : OUT STD_LOGIC;
    Addr_adv_ld_n_reg : OUT STD_LOGIC;
    Addr_reg : OUT STD_LOGIC_VECTOR(17 downto 0);
    Data_in_reg : OUT STD_LOGIC_VECTOR(17 downto 0);
    Data_out_reg : OUT STD_LOGIC_VECTOR(17 downto 0);
    Dm_reg : OUT STD_LOGIC_VECTOR(3 downto 0)
    );
    end component;

    signal addr_adv_ld_n_reg : STD_LOGIC;
    signal addr_reg : STD_LOGIC_VECTOR(17 downto 0);
    signal data_in_reg : STD_LOGIC_VECTOR(17 downto 0);
    signal delay_data_in : STD_LOGIC_VECTOR(17 downto 0);
    signal delay_rw_n : STD_LOGIC_VECTOR(17 downto 0);
    signal dm_reg : STD_LOGIC_VECTOR(3 downto 0);
    signal lb_data_out : STD_LOGIC_VECTOR(17 downto 0);
    signal rd_wr_n_reg : STD_LOGIC;
    signal read_data : STD_LOGIC_VECTOR(17 downto 0);


    BEGIN



    b2v_ADDR_CTRL_OUT1 : addr_ctrl_out
    GENERIC MAP(ASIZE => 18,BWSIZE => 4)
    PORT MAP(Clk => CLK,
    Reset => RESET,
    Lb_rw_n => rd_wr_n_reg,
    Lb_adv_ld_n => addr_adv_ld_n_reg,
    Lb_addr => addr_reg,
    Lb_bw => dm_reg,
    Ram_rw_n => RW_N,
    Ram_adv_ld_n => ADV_LD_N,
    Ram_addr => SA,
    Ram_bw_n => BW_N);

    b2v_DATA_INOUT1 : data_inout
    GENERIC MAP(BWSIZE => 4,DSIZE => 18)
    PORT MAP(Clk => CLK,
    Reset => RESET,
    Ctrl_in_rw_n => delay_rw_n,
    Data_in => delay_data_in,
    Dq => DQ,
    Read_data => read_data);

    b2v_inst2 : pipe_delay
    GENERIC MAP(BWSIZE => 4,DSIZE => 18,FLOWTHROUGH => 0)
    PORT MAP(Clk => CLK,
    Reset => RESET,
    Lb_rw_n => rd_wr_n_reg,
    Lb_data_in => data_in_reg,
    Ram_data_out => read_data,
    Delay_data_in => delay_data_in,
    Delay_rw_n => delay_rw_n,
    Lb_data_out => lb_data_out);

    b2v_PIPE_STAGE1 : pipe_stage
    GENERIC MAP(ASIZE => 18,BWSIZE => 4,DSIZE => 18)
    PORT MAP(Clk => CLK,
    Reset => RESET,
    Rd_wr_n => RD_WR_N,
    Addr_adv_ld_n => ADDR_ADV_LD_N,
    Addr => ADDR,
    Data_in => DATA_IN,
    Data_out => lb_data_out,
    Dm => DM,
    Rd_wr_n_reg => rd_wr_n_reg,
    Addr_adv_ld_n_reg => addr_adv_ld_n_reg,
    Addr_reg => addr_reg,
    Data_in_reg => data_in_reg,
    Data_out_reg => DATA_OUT,
    Dm_reg => dm_reg);

    END;
    ALuPin, Jun 25, 2004
    #1
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  2. (ALuPin) wrote in message news:<>...

    > ENTITY zbt_ctrl_top IS
    > port
    > (
    > CLK : IN STD_LOGIC;
    > RESET : IN STD_LOGIC;


    This entity has no generic clause.
    You can't do a generic map on an instance
    when the base entity has no generic to map.

    Something like:

    ENTITY zbt_ctrl_top IS
    GENERIC (ASIZE : natural;BWSIZE: natural);
    port( ...


    Also consider using direct instances
    to elimainate the component declarations.

    -- Mike Treseler
    Mike Treseler, Jun 25, 2004
    #2
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