Re: Generic Parameters in top-level file

Discussion in 'VHDL' started by ALuPin, Jun 25, 2004.

  1. ALuPin

    ALuPin Guest

    In my toplevel-file (schematic) the components do have
    Generic width on their ports (I am using QuartusII software).

    All components symbols have a PARAMATERS BOX in which the value
    of the Generics can be defined (Mark Symbol of component --> Symbol
    Properties ---> Parameter Name: DSIZE / Setting:18 ...

    When I create a VHDL file of the schematic top level file
    (Quartus : ---> FILE ---> CREATE ---> VHDL File)
    you get the VHDL file shown above.
    It seems that Quartus has replaced the Generic input/output widths
    of the components. But still there is a GENERIC MAP statement
    in the created VHDL file.
    And of course the compiler will not be able to handle that if
    there is no Generic Declaration in the VHDL top level file.

    What to do?

    Thank you for your help.
    ALuPin, Jun 25, 2004
    #1
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