Re: GHDL and Tristate Busses

Discussion in 'VHDL' started by Enrik Berkhan, Jan 10, 2012.

  1. Hi,

    Rob Doyle <> wrote:
    > I have a simple tristate bus simulation that I can't make work with
    > GHDL. Attached.
    >
    > It generates the following error:
    >
    > error: invalid memory access (dangling accesses or stack size too small)
    > error: simulation failed
    >
    > I've tried increasing the stack size but it still fails.
    >
    > It seems to work with the Xilinx Webpack....
    >
    > Any clues?


    Your testbench will run for ever. Looks like your GHDL version leaks
    memory in this case or something. Either make the clock stop after some
    time or tell ghdl to stop after some time like this:

    $ ./test_asdf --stop-time=1us

    On my system (Debian 6.0.3 x86_64, GHDL 0.29 from the distribution), your code
    runs without a growing process. Modelsim is happy, too.

    Enrik
    Enrik Berkhan, Jan 10, 2012
    #1
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