Re: [GHDL] Solution to --> primary unit "std_logic_arith" not foundin library "ieee"

Discussion in 'VHDL' started by Bart Fox, Sep 15, 2013.

  1. Bart Fox

    Bart Fox Guest

    > If anyone has had this problem, just do this:
    > ghdl -a --ieee=synopsys x.vhd

    I avoid the proprietary and obsolete std_logic_arith/std_logic_unsigned
    everywhere.

    I use the "official" ieee.numeric_std.all for arithmetic.
    Don't mix the librarys. So unsigned and signed types are usable on ports
    without headaches.

    regards,
    Bart Fox
     
    Bart Fox, Sep 15, 2013
    #1
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  2. Bart Fox

    pini

    Joined:
    Jul 10, 2007
    Messages:
    11
    Location:
    israel
    To use arithmetics I use the following:

    use ieee.numeric_std.all;
    use ieee.STD_LOGIC_UNSIGNED.conv_integer;
    use ieee.STD_LOGIC_UNSIGNED."+";
    ...
    --average
    average_i <=
    average_p(8 downto 1) when fsm_ps(c_loc_ave0) = '1' else average_q;
    average_p <= std_logic_vector(
    unsigned('0' & mem_do(39 downto 32)) + unsigned('0' & h_ttl_q)
    );

    ...
    if [ "$skip" = "f" ] ; then
    ghdl -i --workdir=work --ieee=synopsys tb_rx_top.vhd rx_top.vhd ip_ttl_extract.vhd ip_ttl_control.vhd mem_model.vhd <& cmp.log
    grep vhd cmp.log < /dev/null
    if [ $? -eq 0 ] ; then
    echo "compilation failed"
    cat cmp.log
    exit 1
    else
    ghdl -m --workdir=work --ieee=synopsys tb_rx_top
    ...

    The compile script is described in detail at:
    h===://bknpk.no-ip.biz/my_web/SDIO/ip_ttl_filter_sim_scr.html
    The code is explained:
    h===://bknpk.no-ip.biz/my_web/SDIO/ip_ttl_filter_vhdl_averaege.html
     
    pini, Sep 15, 2013
    #2
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  3. Bart Fox

    Vignesh2207

    Joined:
    Mar 19, 2014
    Messages:
    1
    Do anyone face this problem,
    I receive error when i compile files in GHDL, I get "c:\...\ghdl -m tb_freqc tb_freqc.vhd:40:10 primary unit "math_real" not found in library "ieee", i didnot miss any libraries and logics, how to debugg it.... I tried the above post still i get bugs,

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use ieee.math_real.all;

    library work;
    use work.tdc_package.all;

    entity tb_freqc is
    generic(
    g_COUNTER_WIDTH : positive := 20;
    g_TIMER_WIDTH : positive := 16;
    g_CLK_PERIOD : real := 8.0;
    g_CLK_M_PERIOD : real := 4.36
    );
    end entity;

    architecture tb of tb_freqc is

    signal clk : std_logic;
    signal reset : std_logic;
    signal clk_m : std_logic;
    signal start : std_logic;
    signal ready : std_logic;
    signal freq : std_logic_vector(g_COUNTER_WIDTH-1 downto 0);

    signal end_simulation : boolean := false;

    begin
    cmp_dut: tdc_freqc
    generic map(
    g_COUNTER_WIDTH => g_COUNTER_WIDTH,
    g_TIMER_WIDTH => g_TIMER_WIDTH
    )
    port map(
    clk_i => clk,
    reset_i => reset,
    clk_m_i => clk_m,
    start_i => start,
    ready_o => ready,
    freq_o => freq
    );

    process
    begin
    clk <= '0';
    wait for g_CLK_PERIOD/2.0 * 1 ns;
    clk <= '1';
    wait for g_CLK_PERIOD/2.0 * 1 ns;
    if end_simulation then
    wait;
    end if;
    end process;

    process
    begin
    clk_m <= '0';
    wait for g_CLK_M_PERIOD/2.0 * 1 ns;
    clk_m <= '1';
    wait for g_CLK_M_PERIOD/2.0 * 1 ns;
    if end_simulation then
    wait;
    end if;
    end process;

    process
    variable v_freq_int : integer;
    variable v_ratio_actual : real;
    variable v_ratio_measured : real;
    variable v_error : real;
    variable v_max_error : real;
    begin
    start <= '0';
    reset <= '1';
    wait until rising_edge(clk);
    reset <= '0';
    wait until rising_edge(clk);

    start <= '1';
    wait until rising_edge(clk);
    wait for 1 ns;
    assert ready = '0' severity failure;
    start <= '0';
    wait until ready = '1';
    v_freq_int := to_integer(unsigned(freq));
    v_ratio_actual := g_CLK_PERIOD/g_CLK_M_PERIOD;
    v_ratio_measured := real(v_freq_int)/real(2**g_TIMER_WIDTH-1);
    v_error := abs(v_ratio_measured-v_ratio_actual);
    v_max_error := 1.0/real(2**g_TIMER_WIDTH-1);
    report "Raw measured value: " & integer'image(v_freq_int);
    report "g_CLK_PERIOD/g_CLK_M_PERIOD (actual): " & real'image(v_ratio_actual);
    report "g_CLK_PERIOD/g_CLK_M_PERIOD (measured): " & real'image(v_ratio_measured);
    report "Error: " & real'image(v_error) & " (maximum: " & real'image(v_max_error) & ")";
    assert v_error <= v_max_error severity failure;

    report "Test passed.";
    end_simulation <= true;
    wait;
    end process;
    end architecture;


    Is this a problem of operating system because I work on Windows and i modify the shell extension files into batch files and then i compile, whether i should work in linux...

    my batch file is,

    ghdl -i ../../package/tdc_package.vhd ../../vhd/tdc_psync.vhd ../../vhd/tdc_freqc.vhd tb_freqc.vhd
    ghdl -m tb_freqc
    ghdl -r tb_freqc --vcd=tb_freqc.vcd
    gtkwave tb_freqc.vcd

    Please reply me,

    Thanks in advance,
     
    Last edited: Mar 19, 2014
    Vignesh2207, Mar 19, 2014
    #3
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