Re: How do variables get synthesized in this case?

Discussion in 'VHDL' started by Jacko, Mar 19, 2009.

  1. Jacko

    Jacko Guest

    On 19 Mar, 16:15, Dave <> wrote:
    > On Mar 18, 1:47 pm, Jacko <> wrote:
    >
    >
    >
    >
    >
    >
    >
    > > It will match your code in boolean logic function of registered values
    > > if all critical sensitivities are included. It may not match your code
    > > if you miss one, hence the warning. All non critical ones may produce
    > > a warning, but would not change the functioning of the code.

    >
    > > So there are 3 types of referred to signal.

    >
    > > process(clk)
    > >   fart <= smelly;
    > >   nose <= fn(fart);
    > > end process;

    >
    > > in this instance having fart in the sensitivity list is pointless but
    > > still makes a warning.

    >
    > > with process(clk,smelly) everything will simulate correctly but still
    > > cause a warning.

    >
    > > with process(clk,fart) changes in smelly would not be relevant, and
    > > could be register delayed through clk.

    >
    > Correct me if I'm wrong here, but if 'fart' were not in the
    > sensitivity list, wouldn't it be that 'nose' wouldn't get the correct
    > value? Since 'fart' is not updated until a delta cycle later, the
    > process would need to fire again for 'nose' to get the results of the
    > function for the new 'fart'. But without 'fart' in the list, the
    > process won't fire upon 'fart' changing, and 'nose' represents the
    > value from the old 'fart'.


    "What are tou doing Dave?" - .......

    But seriously that is wahat I would expect, hence power transitions on
    smelly or indirectly on nose would be avoided as the sim would
    suggest, but sythesis may emit a warning and still make a circuit
    which consumes said power.

    cheers jacko
    Jacko, Mar 19, 2009
    #1
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