Re: How to change Read Only Constraint to Read-Write

Discussion in 'VHDL' started by Isaac, Jul 10, 2003.

  1. Isaac

    Isaac Guest

    Sorry , I changes my code to Input .......
    So please read SR_DATA_IO_int (13 downto 0) as Input (13 downto 0)

    Cheers

    Isaac


    Allan Herriman <> wrote in message news:<>...
    > On 9 Jul 2003 11:00:32 -0700, (Isaac) wrote:
    >
    > >Yes ALLAN I am Sure I am using different bits
    > >
    > >
    > >E.g
    > >
    > >This VHDL code I tried but in PAR file no pin assignment for signal 13 to 7
    > >
    > > process(CLK_2X,SR_ADDR_IO_int,SR_DATA_IO_int,SR_IRD_int,SR_IWR_int,SR_IVCS_V3_int)
    > >begin
    > > if RISING_EDGE(CLK_2X) then
    > > if SR_IVCS_V3_int = '0' then
    > > if SR_IWR_int = '0' then
    > > if SR_ADDR_IO_int = "001100" then
    > > LED_V3_int <= SR_DATA_IO_int(13 downto 7);
    > > end if;
    > > end if;
    > > end if;
    > > end if;
    > >end process P_SRAM2LED;

    >
    >
    > It's hard to say exactly what's going on, because you didn't include
    > the right bits of VHDL (i.e. the signal declarations).
    > Which signal is related to the "INPUT" signal in your first post?
    >
    > The only signal is likely to be of type std_logic_vector is
    > SR_ADDR_IO_int, and that is only six bits long. Hmmm, the error
    > messages indicated that the six least signficant bits of INPUT were
    > used.
    > Do you have an assignment like:
    > SR_ADDR_IO_int <= INPUT(5 downto 0);
    > anywhere in your code?
    >
    > You also might want to fix the sensitivity list.
    >
    > Regards,
    > Allan.
    Isaac, Jul 10, 2003
    #1
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