Re: I can't set inout port in vhdl code

Discussion in 'VHDL' started by rickman, Nov 12, 2004.

  1. rickman

    rickman Guest

    suntthekid wrote:
    >
    > Hello,
    > I have a problem about set up inout port when i simulate vhdl code It
    > is not work
    > so i want to know how to write vhdl code ( set pin to inout and
    > it is work) also i try to use tristate but It is not work too. maybe i
    > miss something in the code and i don't know. help me please


    You might also try posting this to comp.lang.vhdl. What the heck, I'll
    do it for you...

    --

    Rick "rickman" Collins


    Ignore the reply address. To email me use the above address with the XY
    removed.

    Arius - A Signal Processing Solutions Company
    Specializing in DSP and FPGA design URL http://www.arius.com
    4 King Ave 301-682-7772 Voice
    Frederick, MD 21701-3110 301-682-7666 FAX
    rickman, Nov 12, 2004
    #1
    1. Advertising

  2. Mike Treseler, Nov 12, 2004
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. cruzin
    Replies:
    2
    Views:
    4,104
    PO Laprise
    Jan 23, 2004
  2. Replies:
    5
    Views:
    11,586
  3. =?ISO-8859-15?Q?Fr=E9d=E9ric_Lochon?=

    connecting std_logic inout ports and std_logic_vector inout port

    =?ISO-8859-15?Q?Fr=E9d=E9ric_Lochon?=, Nov 6, 2007, in forum: VHDL
    Replies:
    3
    Views:
    838
  4. Ken

    inout to inout

    Ken, May 9, 2008, in forum: VHDL
    Replies:
    2
    Views:
    579
    Aiken
    May 9, 2008
  5. THurkmans
    Replies:
    14
    Views:
    1,772
    Mike Treseler
    Aug 11, 2009
Loading...

Share This Page