Re: I/Os with Cypress chip

Discussion in 'VHDL' started by Charles M. Elias, Jul 16, 2003.

  1. "Brad Smallridge" <> wrote in message news:<>...
    > Dear folks,
    >
    > I am a Cypress user and have had the trouble of laying out a board using 134
    > of what I thought were 136 available I/O lines going into the device. Eight
    > of these lines were global control or global clocks. I had thought that I
    > could use all of them but the Warp 6.2 only lets me use 128 I/Os. What
    > gives? Is there a special declaration I should be using for the global pins?
    > Do I only get 128 I/Os even though there are 136 I/O pins?
    >
    > Thanks,
    >
    > Brad
    >
    > P.S Details of my discussion with Cypress below:
    >
    > Created at: 06/20/03 03:45 PM
    >
    > Part Number: Delta 39K
    > Product: Programmable Logic > Programmable Logic Devices
    > Subject: Error with Max IO
    > Description: I am running Warp6.2 for a 39k100 and get error EMP043
    > Resource Limit Maximum Number of IO Cells Exceeded (max=128, needed 134)
    > although I believe this chip should have enough IO.
    >
    > Brad
    >
    > Attachments:
    >
    > Interactions
    >
    > Cypress Response 07/15/03 08:03 AM | Web
    > Hi Brad,
    >
    > I hope we have fully addressed your inquiry. I am closing this case for now,
    > if you require further assistance on this issue please re-open this case
    > (using the radio button for Status, Open, and clicking Submit) and we will
    > be glad to assist you. For all other inquiries please open a new case.
    >
    >
    > Thank you for using Cypress products,
    >
    > Cypress Applications Support
    >
    >
    > Cypress Response | 07/10/03 02:51 PM | Web
    > Hi Brad,
    >
    > The global clock and control signal pins are declared as inputs (for OE)
    > Warp will route these signals as in the 11c signal in your design.
    >
    >
    > Cypress Applications Support
    >
    >
    > Customer Comment Brad Smallridge | 07/10/03 11:33 AM | Web
    > Are there some sort of other pin type assignemnts similar to in, out, or
    > inout that should be used with the global clock and global control pins?
    >
    > Cypress Response | 07/07/03 09:33 AM | Web
    > Hi Brad,
    >
    > Sorry for all the confusion.
    >
    > In reference to your response:
    >
    > The data sheets state that I have 136 IOs available. Is there some sort of
    > internal architecture that limits me to 128 IOs? What pins may I or may I
    > not use?
    >
    > Page 2 of the datasheet states that of the 208 packages. " Device Package
    > Offering and I/O Count Including Dedicated Clock and Control Inputs", is
    > 136.
    >
    > Pages 50 thru 56 of the datasheet explain the pins and their functions for
    > the CY39100V208-200NTC package. If you count the number of pins that can
    > function as I/O's there are 128. Depending how you configure the I/O's this
    > number decreases.
    >
    > Please see application note: Delta39K and Quantum38K I/O Standards and
    > Configurations
    >
    > I/O Standards and Configurations
    >
    >
    > Thank you for your patience
    >
    >
    > Cypress Applications Support
    >
    >
    >
    >
    > Customer Comment Brad Smallridge | 07/03/03 12:48 PM | Web
    > This reply seems non-responsive. The data sheets state that I have 136 IOs
    > available. Is there some sort of internal architecture that limits me to 128
    > IOs? What pins may I or may I not use? I think I need a better answer since
    > I have already committed to, and spent money on, a hardware design.
    >
    >
    > Cypress Response | 07/02/03 01:51 PM | Web
    > Hi Brad,
    >
    > The pin attributes in your design are fine. Whether or not the design can be
    > fitted to the device depends on the rest of your design which you have
    > commented out. There are too many floating signals to determine if this
    > design as coded can be compiled to fit the device.
    >
    > From what I have been able to determine, you will probably not have enough
    > I/O's to support your design.
    >
    >
    > Thank you for your patience
    >
    >
    > Cypress Applications Support
    >
    >
    > Customer Comment Brad Smallridge | 07/02/03 09:24 AM | Web
    > I am not using VCCIO for signals. Perhaps you can look at my VHD pin list
    > and tell me what pins I can not use?
    >
    > Cypress Response | 06/30/03 09:09 AM | Web
    > Hi Brad,
    >
    > I did try to contact you, I left a msg on your voice-mail.
    >
    > I hope we have fully addressed your inquiry. I am closing this case for now,
    > if you require further assistance on this issue please re-open this case
    > (using the radio button for Status, Open, and clicking Submit) and we will
    > be glad to assist you. For all other inquiries please open a new case.
    >
    >
    > Thank you for using Cypress products,
    >
    > Cypress Applications Support
    >
    >
    > Cypress Response | 06/27/03 03:20 PM | Web
    > Hi Brad,
    >
    > Thank you for using the Cypress On-Line ConnectionCenterT. In reference to:
    >
    >
    > Error EMP043 Resource Limit Maximum Number of IO Cells Exceeded (max=128,
    > needed 134) although I believe this chip should have enough IO.
    >
    > Ans: The available number of I/O's for this device is 128, the additional 8
    > I/O's (VCCIO) are for power to the I/O banks and not for signals.
    >
    >
    > Note:
    >
    > If you limit your design to the use of 128 I/O's it will compile
    >
    >
    >
    > Thank you for your patience
    >
    > Cypress Applications Support
    >
    >
    > Customer Comment Brad Smallridge | 06/27/03 12:03 AM | Web
    > 1) CY39100V208B-200NTC
    > 2) no other errors
    >
    > VHD file is attached
    > test08.vhd
    >
    >
    > Cypress Response | 06/23/03 10:27 AM | Web
    > Hi Brad,
    >
    > We are presently looking into your case and will respond as soon as
    > possible. I want to clarify your issue, "Error with Max IO":
    >
    > 1) What is the entire part description of the device that you are targeting?
    >
    > 2) Are their any other errors being generated by the compiler?
    >
    >
    > Please include your design files that we may further investigate this issue.
    >
    >
    > Thank you for your patience
    >
    > Cypress Applications Support


    Brad,

    Using the Cypress data, sheet I count 128 IO pins, 4 global clock pins
    and 4 global control pins. This does add up to 136 "IO" pins.
    However, the global clock pins can be used only for clock signals and,
    according to the data sheet, "There are four dedicated inputs
    (GCTI[3:0]) that are used as Global Control Signals available to every
    IO cell. These global control signals may be used as output enables,
    register resets, and register clock enables as shown in figure 8." So
    the global control signals are dedicated inputs and the global clocks
    can be used only for clocks. This should explain why you are not able
    to use 136 pins for general purpose IO.

    Best regards,

    Charles
     
    Charles M. Elias, Jul 16, 2003
    #1
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  2. "Brad Smallridge" <> wrote in message news:<>...
    > It would appear, however, that I can get the Global Signals to work as
    > inputs. But when I do, then I loose an I/O. That doesn't seem right. Like
    > buying a three input OR gate and only being able to use two of the inputs at
    > any one time.
    >
    > Brad


    Brad,

    I can't explain the loss of other I/O pins when the global signals are
    used. This could be a fitter problem. If it is, I wish you the best
    of luck trying to get Cypress to fix it.

    We are having a number of difficulties with the 39K device fitter.
    One of the scariest ones is this: We successfully fitted a design and
    then wished to make a change that involved adding a pin. Since the
    prototype board is already wired, we "fixed" the previously fitted
    pins prior to fitting the design with the added pin. The design does
    not fit. As a sanity check, we removed the new signal from the design
    and tried to fit it with the pins "fixed" as the fitter previously
    assigned them. The design will not fit. If we remove the compiler
    directive that keeps the pinout from changing, the design will fit and
    has the same pinout that we instructed it to keep. This does not bode
    well for future designs where one wants to make a change without
    changing the pin assignments previously made.

    I am sorry to report that Cypress seems unwilling to fix this and
    several other problems with the 39K fitter.

    Best regards,

    Charles
     
    Charles M. Elias, Jul 18, 2003
    #2
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