Re: infinite synthesize time

Discussion in 'VHDL' started by Colin Paul Gloster, Feb 14, 2006.

  1. On Tue, 14 Feb 2006 00:07:50 -0800, Leow Yuan Yeow posted:

    "I was trying to synthesize this vhdl code but it seems to take forever; I
    had it running on a com for 4 days and it shows no signs of finishing. Any
    idea whether it is a code problem? I am using Xilinx ISE 7.1 and the code
    is
    fine under syntax checking and behavioural simulation using Modelsim."

    Check your memory usage when attempting to synthesize. Xilinx WebPACK can
    slow down dramatically if virtual memory is being used.
    Colin Paul Gloster, Feb 14, 2006
    #1
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  2. Colin Paul Gloster wrote:
    > On Tue, 14 Feb 2006 00:07:50 -0800, Leow Yuan Yeow posted:
    >
    > "I was trying to synthesize this vhdl code but it seems to take forever; I
    > had it running on a com for 4 days and it shows no signs of finishing. Any
    > idea whether it is a code problem? I am using Xilinx ISE 7.1 and the code
    > is
    > fine under syntax checking and behavioural simulation using Modelsim."
    >
    > Check your memory usage when attempting to synthesize. Xilinx WebPACK can
    > slow down dramatically if virtual memory is being used.


    The OP might also try synthesizing
    the sub-entities from the bottom
    up to find the sticky wicket.

    -- Mike Treseler
    Mike Treseler, Feb 14, 2006
    #2
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  3. Colin Paul Gloster

    Rob Dekker Guest

    Hi Colin,

    Rather than wasting another couple of days, can you post the VHDL so we
    can look through potential nasty constructs and run it on other synthesis tools ?

    Rob

    "Colin Paul Gloster" <> wrote in message news:...
    > On Tue, 14 Feb 2006 00:07:50 -0800, Leow Yuan Yeow posted:
    >
    > "I was trying to synthesize this vhdl code but it seems to take forever; I
    > had it running on a com for 4 days and it shows no signs of finishing. Any
    > idea whether it is a code problem? I am using Xilinx ISE 7.1 and the code
    > is
    > fine under syntax checking and behavioural simulation using Modelsim."
    >
    > Check your memory usage when attempting to synthesize. Xilinx WebPACK can
    > slow down dramatically if virtual memory is being used.
    >
    Rob Dekker, Feb 22, 2006
    #3
  4. Rob Dekker wrote:
    > Hi Colin,
    >
    > Rather than wasting another couple of days, can you post the VHDL so we
    > can look through potential nasty constructs and run it on other synthesis tools ?


    Leow Yuan Yeow was the original poster,
    apparently by email to Rob.

    -- Mike
    Mike Treseler, Feb 23, 2006
    #4
  5. Mike Treseler wrote:
    > Rob Dekker wrote:
    >> Hi Colin,
    >>
    >> Rather than wasting another couple of days, can you post the VHDL so we
    >> can look through potential nasty constructs and run it on other
    >> synthesis tools ?

    >
    > Leow Yuan Yeow was the original poster,
    > apparently by email to

    Colin

    -- Mike Treseler
    Mike Treseler, Feb 23, 2006
    #5
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