Re: infinite synthesize time

Discussion in 'VHDL' started by Ben Jones, Feb 15, 2006.

  1. Ben Jones

    Ben Jones Guest

    "Leow Yuan Yeow" <> wrote in message
    news:...
    > Hi there,


    > I was trying to synthesize this vhdl code but it seems to take
    > forever; I had it running on a com for 4 days and it shows no
    > signs of finishing. Any idea whether it is a code problem?


    XST often has difficulty with looping constructs in procedures and
    functions, although usually a single loop (no nesting) will not cause
    problems. You'll probably find it will be using a very large amount of
    system memory, and it thus paging a lot and slowing itself down even more.

    Code-wise, I have not seen such a huge if-elsif-elsif statement for a long
    time - coupled with your very large one-hot-encoded state vectors, it looks
    like there is a very large amount of logic here. So even though your VHDL
    may be perfectly correct, it might be very hard to synthesize.

    You could try a different synthesis tool if you have one available. You
    might also want to try breaking down your circuit into smaller pieces and
    see if that helps. In any event I would suggest opening a webcase with
    Xilinx and submitting your design for analysis.

    -Ben-
     
    Ben Jones, Feb 15, 2006
    #1
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