Re: Is this OK?

Discussion in 'VHDL' started by Charles M. Elias, Jul 22, 2003.

  1. (Matt Gessner) wrote in message news:<>...
    > Hi, all,
    >
    > I have a question about whether the following is a) synchronous (I believe
    > it is) and b) advisable:
    >
    > signal counter: std_logic_vector (4 downto 0);
    > signal clk: std_logic;
    > signal cclk: std_logic;
    >
    > processa: process (clk) is
    > begin
    > if rising_edge (clk) then
    > counter <= counter + 1;
    > end if;
    > end process;
    >
    > cclk <= counter (4);
    >
    > processb: process (cclk) is
    > begin
    > if rising_edge (cclk) then
    > null; -- do something interesting
    > end if;
    > end process;
    >
    > Part of me screams "No, don't do it!" because I'm making a clock
    > out of something that's not //really// a clock. Is this is a problem?
    >
    > Essentially, I'm scaling clk down by 8. In general, is this the
    > way to do this? Is there something more advisable?
    >
    > I look forward to your insights.
    >
    > Thanks -- Matt

    Matt,

    I don't think your logic is wrong, but here is another (generic)
    approach. This is derived from From FAQ complang.vhdl part 1. I
    added some features that can be omitted if not needed. It produces a
    symmetric output waveform if "Modulus" is even, otherwise it stays low
    for one input clock period
    longer than it stays high. Below is the entity/architecture for the
    clock component. If you don't need the enable or reset, just omit
    them from the component declaration.

    --------------------------------------------------------------------------------
    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    --------------------------------------------------------------------------------
    entity clock_divider is
    generic(modulus: in positive range 2 to integer'high);
    port( clk_in : in std_logic;
    enable : in std_logic := '1';
    reset : in std_logic := '0';
    clk_out : out std_logic );
    end clock_divider;

    architecture behavior of clock_divider is
    begin
    process (clk_in, reset, enable )

    variable count: natural range 0 to modulus - 1;

    begin
    if reset = '1' then
    count := 0;
    clk_out <= '0';
    elsif rising_edge( clk_in ) then
    if enable = '1' then
    if count = modulus - 1 then
    count := 0;
    else
    count := count + 1;
    end if; --count = modulus - 1
    else
    count := count;
    end if; --enable = '1'
    if count >= modulus/2 then
    clk_out <= '0';
    else
    clk_out <= '1';
    end if; --count >= modulus/2
    end if; --rising_edge( clk_in )
    end process;
    end behavior;
    Charles M. Elias, Jul 22, 2003
    #1
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