Re: Is this OK?

Discussion in 'VHDL' started by Jerold Green, Jul 23, 2003.

  1. Jerold Green

    Jerold Green Guest

    This is not synchronous. You are using a ripple carry as a clock. This is
    a bad idea because this clock is slightly delayed. If the inputs to
    processb are clocked by clk, they may be in transition when cclk changes.

    To make this synchronous, make a carry output
    carry <= '1' when counter = "1111";


    Then in processb, use carry as an enable:
    processb: process (clk) is
    begin
    if rising_edge (clk) then
    if (carry = '1') then
    null; -- do something interesting
    end if;
    end if;
    end process;

    This is fully synchronous.

    "Matt Gessner" <> wrote in message
    news:...
    > Hi, all,
    >
    > I have a question about whether the following is a) synchronous (I believe
    > it is) and b) advisable:
    >
    > signal counter: std_logic_vector (4 downto 0);
    > signal clk: std_logic;
    > signal cclk: std_logic;
    >
    > processa: process (clk) is
    > begin
    > if rising_edge (clk) then
    > counter <= counter + 1;
    > end if;
    > end process;
    >
    > cclk <= counter (4);
    >
    > processb: process (cclk) is
    > begin
    > if rising_edge (cclk) then
    > null; -- do something interesting
    > end if;
    > end process;
    >
    > Part of me screams "No, don't do it!" because I'm making a clock
    > out of something that's not //really// a clock. Is this is a problem?
    >
    > Essentially, I'm scaling clk down by 8. In general, is this the
    > way to do this? Is there something more advisable?
    >
    > I look forward to your insights.
    >
    > Thanks -- Matt
    Jerold Green, Jul 23, 2003
    #1
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