Re: Is this OK?

Discussion in 'VHDL' started by Rain Adelbert, Jul 28, 2003.

  1. I think this is absolutely fine. You get the divided clock out from
    flip-flop and it should be clean.
    The other thing is, thechnology specific, if your flip-flop is strong enough
    to drive the clock line. Normally the synthesis tool solves this for you,
    otherwise insert a clock buffer.


    "Matt Gessner" <> wrote in message
    > Hi, all,
    > I have a question about whether the following is a) synchronous (I believe
    > it is) and b) advisable:
    > signal counter: std_logic_vector (4 downto 0);
    > signal clk: std_logic;
    > signal cclk: std_logic;
    > processa: process (clk) is
    > begin
    > if rising_edge (clk) then
    > counter <= counter + 1;
    > end if;
    > end process;
    > cclk <= counter (4);
    > processb: process (cclk) is
    > begin
    > if rising_edge (cclk) then
    > null; -- do something interesting
    > end if;
    > end process;
    > Part of me screams "No, don't do it!" because I'm making a clock
    > out of something that's not //really// a clock. Is this is a problem?
    > Essentially, I'm scaling clk down by 8. In general, is this the
    > way to do this? Is there something more advisable?
    > I look forward to your insights.
    > Thanks -- Matt
    Rain Adelbert, Jul 28, 2003
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