Re: mapping input/output port

Discussion in 'VHDL' started by Tricky, Oct 15, 2009.

  1. Tricky

    Tricky Guest

    On 15 Oct, 13:14, anal_aviator <> wrote:
    > In my top level i have this:
    >
    > entity user_logic is
    > port
    >         (
    > the_data_I                    : in std_logic_vector(7 downto 0);
    >         the_data_O                    : out std_logic_vector(7 downto 0);
    >         the_data_T                    : out std_logic;
    > );
    >
    > and this ties directly in to the pins
    > Then I want to instigate lower logic
    >
    > component RAM_IF is
    >    generic (
    >  RW :in std_logic;
    >  ram_data_x     : inout byte;          
    > )
    >
    > How do I tie the two together so that ram data ends up going out of  
    > "the_data"
    >
    >         RAM_IF_INST:RAM_IF (
    >     ram_data_x  => ????
    >    RW
    >
    > )


    you have to create a signal that sits in the middle and has the
    ability to drive 'Z' at the inout port when data is coming in, else
    drive it with the output "the_data_0/T".
     
    Tricky, Oct 15, 2009
    #1
    1. Advertising

  2. Tricky

    Tricky Guest

    On 16 Oct, 01:44, anal_aviator <> wrote:
    > On Thu, 15 Oct 2009 22:48:42 +0800, Tricky wrote
    > (in article
    > <>):
    >
    > > On 15 Oct, 13:14, anal_aviator <> wrote:
    > >> In my top level i have this:

    >
    > >> entity user_logic is
    > >> port
    > >>         (
    > >> the_data_I                    : in std_logic_vector(7 dow

    > nto 0);
    > >>         the_data_O                    : out std_l

    >
    > ogic_vector(7 downto 0);
    >
    >
    >
    > >>         the_data_T                    : out

    > std_logic;
    > >>> ;

    >
    > >> and this ties directly in to the pins
    > >> Then I want to instigate lower logic

    >
    > >> component RAM_IF is
    > >>    generic (
    > >>  RW :in std_logic;
    > >>  ram_data_x     : inout byte;          

    >
    > >> How do I tie the two together so that ram data ends up going out of  
    > >> "the_data"

    >
    > >>         RAM_IF_INST:RAM_IF (
    > >>     ram_data_x  => ????
    > >>    RW

    >
    > > you have to create a signal that sits in the middle and has the
    > > ability to drive 'Z' at the inout port when data is coming in, else
    > > drive it with the output "the_data_0/T".

    >
    > Hi,
    > I understand roughly...
    >
    > would this work
    >
    > signal ram_Data :byte;
    >
    > ram_data_x      => ram_data,
    >
    > ......
    >
    >         ram_data_O<=ram_data when ram_re = '0' else (others=>'0');
    >         ram_data<=ram_data_I when  ram_we = '0' else (others=>'Z');
    >
    > ram_data_T <= ram_re;
    >
    > or would ram_Data be the wrong type....


    ram_data needs to be a std_logic_vector. if byte is declared as a
    subtype of std_logic_vector then thats fine.
     
    Tricky, Oct 16, 2009
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Ken Morrow
    Replies:
    2
    Views:
    7,949
    Jerold Green
    Jul 26, 2003
  2. kwaj

    Port Mapping

    kwaj, Mar 2, 2004, in forum: VHDL
    Replies:
    1
    Views:
    650
    fabbl
    Mar 2, 2004
  3. tulip
    Replies:
    1
    Views:
    498
    rickman
    Oct 29, 2004
  4. tulip

    area optimized port mapping

    tulip, Nov 3, 2004, in forum: VHDL
    Replies:
    1
    Views:
    488
    Nicolas Matringe
    Nov 3, 2004
  5. john

    port mapping

    john, Dec 13, 2004, in forum: VHDL
    Replies:
    1
    Views:
    709
    Nicolas Matringe
    Dec 14, 2004
Loading...

Share This Page