Re: Mixed clocked/combinatorial coding styles

Discussion in 'VHDL' started by Mike Treseler, Aug 19, 2008.

  1. Jonathan Bromley wrote:
    > OK, so I tried the following synthesis example -
    > various declarations omitted to save space.


    Thanks for all the unbillable hours.

    > All five tools gave correct results, but two tools
    > failed to merge the duplicate registers they had
    > created for count and q. Of course, it is entirely
    > possible that those duplicate registers might be
    > merged later, during place-and-route, as they were
    > indeed exact duplicates.


    I have yet to see a duplicate register
    make it all the way through synthesis,
    but they do sometimes clutter the RTL
    schematic. The "odd" template seems
    to tip the algorithm toward doing the
    merge on the front end.

    -- Mike Treseler
     
    Mike Treseler, Aug 19, 2008
    #1
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