Re: Multiple devices within one ISE project

Discussion in 'VHDL' started by Weng Tianxiang, Mar 8, 2007.

  1. On Mar 6, 8:58 am, Phil Hays <> wrote:
    > Andy Peters wrote:
    > > On Mar 5, 1:11 pm, "Jean Nicolle" <> wrote:
    > >> Is it possible to use an ISE project to compile for multiple devices?

    >
    > >> I happen to have a project that can target two different boards with
    > >> different FPGAs. Most of the files are the same, besides the UCF. Do I
    > >> have to create separate ISE projects? I'd rather have one project with
    > >> different variations. But that doesn't seem supported. Anybody can set
    > >> me wrong?

    >
    > > Use a Makefile.

    >
    > A makefile for this build can be a fairly good answer with dual core
    > computers becoming more common, as the two map and par jobs can be run in
    > parallel. Write a makefile and use:
    >
    > make --jobs=2
    >
    > Make is a cool utility. Can be loaded with the Cygwin package on Windows,
    > and is native on Linux. For more information on make:
    >
    > http://www.gnu.org/software/make/
    >
    > Using make doesn't prevent one from using a Tcl script(s) for the actual
    > builds as Jim suggested. If this was done the makefile might have just two
    > items (it might have more as well):
    >
    > ../bld1/board1.bit : *.vhd *.v board1.ucf build.tcl
    > <tab> xtclsh build.tcl board1
    >
    > ../bld2/board2.bit : *.vhd *.v board2.ucf build.tcl
    > <tab> xtclsh build.tcl board2
    >
    > Some explanation of this makefile:
    >
    > 1) The first line of each item is "the target" : "the sources". Make
    > checks to see that the target is newer than the sources. If not newer or
    > if the target does not exist, then make executes the commands on following
    > lines starting with tab characters.
    >
    > 2) " <tab> " is the tab character. Required by make before every command.
    >
    > 3) xtclsh is the Xilinx Tcl shell, used to execute the script. ISE8.2 or
    > later.
    >
    > 4) build.tcl is the script that builds the designs. This script is
    > expecting a parameter to define which board to target.
    >
    > Tcl is not as trivial to multithread as make is. On the other hand, Tcl is
    > a general purpose language, so it can be used for lots of other tasks that
    > make can't do, such as creating revision or timestamp values to be loaded
    > into registers, parsing report files, multiple .ucf files in a design,
    > etc. For more information on Tcl see:
    >
    > http://www.tcl.tk/about/features.html
    >
    > Or the Tcl section in the Xilinx manual.
    >
    > --
    > Phil Hays (Xilinx, but writing my own words)


    Hi,
    I had already met the situation you are in now 3 years ago.

    The main culprit is that VHDL language lacks the capability of
    handling conditional statements.

    Its drawback of VHDL put small company engineers in a very
    disadvantageous place.

    The reason is in small company, one doesn't have manpower resources to
    develop a conditional statement program to permit VHDL to insert
    conditional statements.

    It is very hard for anyone to imagine without such powerful
    conditional statement handling software, Intel would develop a
    multiple core system.

    I mentioned the problem in VHDL group, but met huge opposing and even
    someone suggested to use C++, C language preprocessor program to
    handle VHDL problem, or use makefile. It is a shame for VHDL language.

    Finally I wrote a software to do the job. Since then, I can easily
    develop several versions for one project using one source file:
    product version, ChipScope debugging version, simulation version and
    so on.

    And more than that, I have put 4 project files into one big file, in
    other words, 4 project files are sharing one big VHDL file.

    Without the similar method, Intel cannot manufacture so many product
    lines.

    Generate/loop statements have very limited capability in reality. For
    example, it can only change signal's width in a module interface, but
    it cannot insert or delete any signals in the module interface.

    Weng
     
    Weng Tianxiang, Mar 8, 2007
    #1
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  2. Weng Tianxiang

    fpgaengineer Guest

    Sounds interesting to me. Would you like to contribute this or make a
    piece of commercial software out of it? I guess it would by no problem
    for the -> small companies to spende some Cents on a tool which saves
    hours of programming time over the months.

    Currently I am handling conditional synthesis (parameters mostly) with
    Excel / Access :)

    Thanks
    J., currently working for a "small company"
     
    fpgaengineer, Mar 12, 2007
    #2
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