Re: Parallel in, Parallel out shift register

Discussion in 'VHDL' started by Vivek Menon, Jun 10, 2011.

  1. Vivek Menon

    Vivek Menon Guest

    Thanks for the tips, I was trying to synthesize a shift register using array slicing. Since that was not working, I tried all the remaining options, ror, sra, srl, etc.

    Here's how I did it finally:

    architecture arch of shift_out is

    -- Signals
    signal shift_t1 : std_logic_vector(1727 downto 0) := (others => '0');

    begin

    process (clk, rst) is
    begin
    if rst = '1' then
    shift_t1 <= (others=>'0');
    elsif rising_edge(clk) then
    if (load = '1') then
    shift_t1 <= in1;
    elsif (shift_en ='1') then
    shift_t1 <= shift_t1(15 downto 0) & shift_t1(1727 downto 16);
    end if ;
    end if;
    end process;

    shift_val <= shift_t1(15 downto 0);

    end architecture arch;
     
    Vivek Menon, Jun 10, 2011
    #1
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